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1,431 Views
Registered: ‎12-01-2016

Zynq simulation

Hi,

 

I am working on Zynq simulation now, but I found it is not easy.

 

BFM can not used in Vivado 2017.

 

Is there any way I can run PS+PL simulation?

 

I want to verify DDR and AXI bus and evaluate the time delay within the whole process.

 

Any one can give me any hint?

 

Thanks a lot.

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2 Replies
Xilinx Employee
Xilinx Employee
1,381 Views
Registered: ‎08-01-2008

Re: Zynq simulation

Zynq BFM will be replaced by Xilinx Zynq Verification IP in CY2017.  For more information please contact your Local Xilinx Sales Contact.

 

Please check this videos and user guide for usage

 

https://www.xilinx.com/video/soc/how-to-use-the-zynq-7000-verification-ip-verify-debug-simulation.html

https://www.xilinx.com/video/hardware/how-to-use-axi-verification-ip-to-verify-debug-design-using-simulation.html

https://www.xilinx.com/products/design-tools/vivado/verification-ip.html#documentation

Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
1,328 Views
Registered: ‎07-30-2007

Re: Zynq simulation

Evaluating time delay in behavioral simulation is not likely the right approach- the model is not cycle-accurate. Consider running in hardware instead.
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