06-13-2016 10:14 AM
I'm trying to find info on the SPI bus controller, specifically the Output setup/hold delays.
I'm not interested in the buffer I/O delays as I have already captured that information in the HyperLynx simulations. I'm looking for the uncertainty in the controller itself.
Can someone point me to the data?
06-13-2016 10:26 AM
06-13-2016 10:36 AM
Often times the clock to output delay is labled output Setup and hold times. I have clock to output for the buffer outputs (LVCMOS 25 8ma), but not when the controller is placing data on the bus in relation to the clk.
Yes there should be margin - but I still need to complete my timing analysis. Are these numbers for the SPI controller set since it is part of the PHY?
06-13-2016 10:40 AM
If it's listed as clock to output delay - that's fine, but I don't see it listed anywhere for the SPI interface - not QSPI, but SPI.
06-13-2016 11:57 PM
checkout TMSPICKO parameter on page 28 of DS187 table 41.
06-14-2016 06:31 AM
Thanks for the info. I had the firmware designer generate the numbers for me. We are using LVCMOS 25 S 8 for the buffers, so are numbers are quite different than the data sheet values (3.3V S 8ma). I'm thinking I should use the generated values with those particular buffers?
06-14-2016 03:28 PM
06-15-2016 07:16 AM
Thanks for the reply. Looking at the schematic, it shows that we are using the PS SPI controller.
I don't have a lot of background in FPGAs, but I'm trying to close the chip to chip timing.
Looking at the data sheet for the PS spi controller, it gives timing information based on LVCMOS 33 S 8 driving a 15pf load. My thought was that I could simulate the LVCMOS 33 S 8 buffer into the 15pf load and compare that to the 2.5 LVCMOS into the same 15pF cap to extract the differences. It seems like the clock to out at the register would be similar regardless of the IO buffer type?
The firmware designer said he couldn't generate a timing report for the PS SPI controller, so I'm trying to figure out how to compensate for the timing in the data sheet vs changing the buffer type.
Thanks for your help!