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Visitor kirk.fabbri
Visitor
6,082 Views
Registered: ‎07-20-2015

Zynq timing numbers

I'm trying to find info on the SPI bus controller, specifically the Output setup/hold delays.

I'm not interested in the buffer I/O delays as I have already captured that information in the HyperLynx simulations. I'm looking for the uncertainty in the controller itself.

 

Can someone point me to the data?

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Teacher muzaffer
Teacher
6,078 Views
Registered: ‎03-31-2012

Re: Zynq timing numbers

For output, the relevant timing number is clock to output delay. Setup/hold is for input signals. In SPI data is captured on the opposite edge it is driven and given the speeds SPI is run at, clk-Q would be quite small compared to the half clock period which would be available.
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Visitor kirk.fabbri
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6,076 Views
Registered: ‎07-20-2015

Re: Zynq timing numbers

Often times the clock to output delay is labled output Setup and hold times. I have clock to output for the buffer outputs (LVCMOS 25 8ma), but not when the controller is placing data on the bus in relation to the clk.

 

Yes there should be margin - but I still need to complete my timing analysis. Are these numbers for the SPI controller set since it is part of the PHY?

 

Thanks,

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Visitor kirk.fabbri
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6,072 Views
Registered: ‎07-20-2015

Re: Zynq timing numbers

If it's listed as clock to output delay - that's fine, but I don't see it listed anywhere for the SPI interface - not QSPI, but SPI.

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Teacher muzaffer
Teacher
6,048 Views
Registered: ‎03-31-2012

Re: Zynq timing numbers

checkout TMSPICKO parameter on page 28 of DS187 table 41.

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Visitor kirk.fabbri
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6,037 Views
Registered: ‎07-20-2015

Re: Zynq timing numbers

Thanks for the info. I had the firmware designer generate the numbers for me. We are using LVCMOS 25 S 8 for the buffers, so are numbers are quite different than the data sheet values (3.3V S 8ma). I'm thinking I should use the generated values with those particular buffers?

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Teacher muzaffer
Teacher
6,014 Views
Registered: ‎03-31-2012

Re: Zynq timing numbers

clock to output is not just the output buffer; it should include the register clock to Q delay too.
One question which comes up is whether you are using the PL SPI controller or PS SPI controller. If PS, you really don't know what kind of IO structure they're using so your numbers may not be meaningful for LVCMS 25/S8. If PL, then you need to time the clock from the DFF.CK pin to the IO, DFF.Q pin to the IO and compute the timing at the IO pins.
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Visitor kirk.fabbri
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5,988 Views
Registered: ‎07-20-2015

Re: Zynq timing numbers

Thanks for the reply. Looking at the schematic, it shows that we are using the PS SPI controller. 

 

I don't have a lot of background in FPGAs, but I'm trying to close the chip to chip timing.

 

Looking at the data sheet for the PS spi controller, it gives timing information based on LVCMOS 33 S 8 driving a 15pf load. My thought was that I could simulate the LVCMOS 33 S 8 buffer into the 15pf load and compare that to the 2.5 LVCMOS into the same 15pF cap to extract the differences. It seems like the clock to out at the register would be similar regardless of the IO buffer type? 

 

The firmware designer said he couldn't generate a timing report for the PS SPI controller, so I'm trying to figure out how to compensate for the timing in the data sheet vs changing the buffer type.

 

Thanks for your help!

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