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Advisor ronnywebers
Registered: ‎10-10-2014

Zynq - using 1 gp master with 10 AXI slaves vs 2 gp master with each 5 axi slaves

I'm thinking of the difference between these 2 Zynq designs :


design 1 : uses only M AXI GP0 interface with 10 AXI slave devices

desing 2 : uses M AXI GP0 and M AXI GP1, each handling 5 AXI slave devices



Q1 : it looks logical to me that design 2 will use more FPGA resources, and I think it will have a potentially higher throughput between the Zynq and FPGA, is that a correct assumption?


Q2 : are there any other tradeoffs / differences between both design 1 and 2?

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