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Participant bpb
Participant
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Registered: ‎09-11-2016

ZynqMP I/O coherence latency

I am not measuring a lower latency when reading from APU cache vs. DDR.

The software passes an address to the block in the PL which then issues a read request and receives the read response. To "cache" the data in the APU, the software writes to the memory address before this process (this pulls it into cache). The "uncached" scenario skips this write.

The block is running at 250MHz.  I measure ~95 cycles between read request and read response for the "uncached" scenario, and 100 cycles for the "cached" scenario.  So, it's actually worse!

ARCACHE = 4b'1111, ARPROT=3b'010. The memory is mapped as NORMAL (not NORMAL_NC or DEVICE) in the A53. The bit to extend the Inner Domain beyond the A53 cluster has been enabled.

I thought I/O coherence was supposed to provide lower latency for reads of cached data?  What am I missing?

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