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Participant
Participant
720 Views
Registered: ‎09-11-2016

ZynqMP slave switch clock

CCI and PS-PL AXI interfaces are clocked by TOPSW_MAIN_CLK ~ 533.33MHz

"slave switches" are clocked by TOPSW_LSBUS_CLK ~ 100MHz

 

Does this mean FPD Main Switch and the switch for HPM0_FPD/HPM1_FPD run at 100MHz?

 

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Participant
Participant
661 Views
Registered: ‎09-11-2016

Re: ZynqMP slave switch clock

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-30-2007

Re: ZynqMP slave switch clock

No.
FPD Main and all switches that drive HP interfaces are TOPSW_MAIN. Only low-speed register interfaces are clocked by TOPSW_LSBUS.