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Registered: ‎04-02-2019

address map for hierarchical designs

I have a design that includes a vivado packaged custom subsystem.    That subsystem has an address map which contains 8 DMA controller AXI blocks and an EMC and GPIO block.   This subsystem has been packaged and has been incorporated into a larger system.


The address map for the incorporating block diagram is 


This address map rolls up the subsystem address map into a single entry DSPFIFO_SAXI_wrapper_1.    If I export this hardware, the HDF file will only show the rolled up entry in the address map for that system, losing the links to the DMA, GPIO and EMC mapped blocks from the subsystem.   This is an issue for the software development side of the project as the subsystem devices do not appear to be part of the system and the BSP does not incorporate them into the design.   There does not seem to be a way to incorporate the address map of a subsystem into the packaged design.

Q: how do I incorporate packaged subsystems into higher level designs so that the underlying address map is not lost?  These must be a way to do this.

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Registered: ‎11-09-2015

Re: address map for hierarchical designs

HI @rutabagazuma 

I do not think this is possible to get the address space of the packaged IP.

However, if this is a packaged IP, then this means that the addresses are fixed and they will only be offsets of the main address

So you can just have a header file in the driver for your IP which defines the offsets.

Product Application Engineer - Xilinx Technical Support EMEA
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