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Observer xminer
Observer
718 Views
Registered: ‎01-31-2018

assignment of M_axi_hpm0/1_fpd

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I pretty new to all of this, and am having a little trouble understanding how the address map gets built.  I am working with the example project for the zcu102 board that contains the zynq, an axi crosspoint, and two slaves.  The cross point is attached to both m_axi_hpmX_fpd masters on the zynq PS block.  When I export the hdf into sdk, it shows that the one slave belongs to the Apus, and the other to the Rpus.  One is on the A0000000 address page, the other on the b0000000.   In the ps/pl customization for the zynq, there is no mention of how those address ranges got mapped to the APU versus the RPU address space.  Is there a default setting that I missed somewhere?  Or am I missing something entirely?

 

The way I discovered any of this, is that I actually added a third slave.  I used the run connection automation to connect it.  The interconnect block got connected as a full 2x3, so both masters should be able to get to all three slaves.  But, then I could not figure out how I would know which master the A53 would use to get to the slaves.  The new slave ended up being listed only in the RPU address map in the system.hdf.  I wanted it to be in the APU map.

 

If someone could point my at the proper documentation, on how the cross switch for the connections for the M_AXI_HPMx_FPD masters are connected, I would really appreciate it.

 

 

 

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Xilinx Employee
Xilinx Employee
997 Views
Registered: ‎07-30-2007

Re: assignment of M_axi_hpm0/1_fpd

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The address maps are set in the addressing chapter of the TRM. Each AXI interface has its own unique range that a master in the PS would address to come out that particular port. That address continues on into the PL, resulting in the mandatory address ranges you see.

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Xilinx Employee
Xilinx Employee
998 Views
Registered: ‎07-30-2007

Re: assignment of M_axi_hpm0/1_fpd

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The address maps are set in the addressing chapter of the TRM. Each AXI interface has its own unique range that a master in the PS would address to come out that particular port. That address continues on into the PL, resulting in the mandatory address ranges you see.

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Observer xminer
Observer
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Registered: ‎01-31-2018

Re: assignment of M_axi_hpm0/1_fpd

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Ah yes, I see it now in figure 10-1.  The S_AXI_HPM0_FPD is a 0xa0000000 and is 512MB, the S_AXI_HPM1_FPD is directly after it a 0xb00000000 and is also 512 MB.

 

That is exactly the information I was looking for.

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