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Visitor jangoris1
Visitor
506 Views
Registered: ‎10-24-2017

axi chip 2 chip

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Hi,

i'm having trouble with my design regarding to the chip 2 chip link between 2 fpga's

* first i do an axi read on the master side of the C2C link, everythings ok

* then i read on the slave side and everything freezes.

* but i can still read (with a different axi master) at the slave side

so i suppose it is the c2c link that causes the freeze, however the c2c link up signal is ok

 

so i have 2 questions:

is there a boot sequence that has to be respected ? Now my slave boots faster than the master

the slave C2C is version 5.0, the master is v4.2 -> can this cause any issues ?

 

Thanks for the input

regards

Jan

 

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Visitor jangoris1
Visitor
525 Views
Registered: ‎10-24-2017

Re: axi chip 2 chip

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Hi,

 

updating vivado for the master project, and thus using the same core version for Chip2Chip seems to have solved the problem.

 

Regards,

Jan 

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Community Manager
Community Manager
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Registered: ‎07-23-2012

Re: axi chip 2 chip

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Can you please share the .xci files? It is recommended to use the IP of same versions because there can be some changes done in the IP across versions (can be found in change log of IP).

Can you please insert ILA and see the status of RRESP in case of freeze?
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Visitor jangoris1
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526 Views
Registered: ‎10-24-2017

Re: axi chip 2 chip

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Hi,

 

updating vivado for the master project, and thus using the same core version for Chip2Chip seems to have solved the problem.

 

Regards,

Jan 

View solution in original post

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