01-13-2020 06:49 AM
Using the AXI DMA IP core.
We have an application were the PL throttles the mm2s stream by periodically asserting the tready signal at a programmable frequency in the range 0 - 20 kHz. We sometimes lose the first entry of the stream.
Does the mm2s tready signal block the upstream data transfer? Or does data get lost somewhere on the way when tready is not asserted on the mm2s interface?
BTW we're using the Zynq 7100, AXI DMA 7.1 and Vivado 2018.3
01-13-2020 08:46 AM
It's typically easiest to fix these kinds of issues when you can see it.
Have you tried simulating the design? You can use the Zynq VIP core to replace the PS in the simulation. The VIP can be used for all of the AXI-Lite setup stuff on the AXI DMA and any other IP.
The next option is to add a System ILA to the design and probe the MM2S port from the AXI DMA. You can trigger on the rising edge of the tready signal.
More than likely, the DMA is providng the first piece of data along with the Tvalid well before the Tready is asserted. Is it possible that the PL code is expecting the first data to arrive after the Tready is asserted instead of being readily available during that first clock cycle?
01-14-2020 01:13 AM
Thanks, our design is indeed expecting the first data to be valid after the tready pulse, I'll modify the design to take the data on the tready instead of after.
01-14-2020 04:32 AM
We modified the design to clock the data on the tready, unfortunately this makes no difference, first entry still lost.
One additional observation we made: If the data producer on the software end "dries up" somewhere in the middle of the transfer length, and then resumes, the a stream element is also lost. So somehow an "empty" DMA core allways discards the first stream element?