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Visitor
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Registered: ‎03-27-2019

axi iic ip example ties scl_o and sda_o to ground in the synthesized schematic

I created a new project in Vivado 2019.1 using an xcku040-ffva1156-3-e part and selected the AXI IIC ip from the catalog.  Created the example project and ran synthesis.  When I checked the schematic, both the scl_o and sda_o lines are grounded in the ip.

After having this same issue in a custom design, it was decided to create the example project to check if a clean project showed the same problem.

Suggestions?  Searches of the knowledge base and forums were unhelpful to me.

iic issue.PNG
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Visitor
Visitor
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Registered: ‎03-27-2019

Re: axi iic ip example ties scl_o and sda_o to ground in the synthesized schematic

Can someone from Xilinx please acknowledge?  Let me know if this is a Vivado bug or if I am misusing the tool.  Thanks.

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-09-2019

Re: axi iic ip example ties scl_o and sda_o to ground in the synthesized schematic

Hi,

Can you please generate the I2C signals from IP to external and capture on CRO and let me know are you getting the signals properly or not. I used VIvado 2019.1 AXI IIC IP and working fine.

Regards,

Venu

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Visitor
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Registered: ‎03-27-2019

Re: axi iic ip example ties scl_o and sda_o to ground in the synthesized schematic

Hi.  The whole reason I started this post was not seeing the scl and sda outputs on my board. 

Apparently you are seeing them on your circuit.  Did you drill down into the schematic to look at the same signal lines I looked at?  Are they wired to ground?  Is this expected behaviour?

Thanks for responding.  Oh, BTW, I had to look up CRO.  Do you mean "Cathode Ray Oscilloscope"?

BW

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Observer
Observer
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Registered: ‎02-01-2018

Re: axi iic ip example ties scl_o and sda_o to ground in the synthesized schematic

hi, I meet same problem in my project. I get '0' from SDA/SCL signal on board by CRO. Then I check the IP schematic, and find the sda_o and scl both connect to GND.

image.png

In axi_iic_v2_0_vh_rfs.vhd of the IP , the  scl_o and sda_o is always '0'.

----------------------------------------------------------------------------

   -- SCL Tristate driver controls for open-collector emulation

   ----------------------------------------------------------------------------

   Scl_T <= '0' when scl_cout_reg = '0'

                     -- Receive fifo overflow throttle condition

                     or Ro_prev = '1'

                     -- SDA changing requires additional setup to SCL change

                     or (sda_setup = '1' )

                     -- Restart w/ transmit underflow prevention throttle

                     -- condition

                     or rsta_tx_under_prev = '1'  else

            '1';

 

   Scl_O <= '0';

   ----------------------------------------------------------------------------

   -- SDA Tristate driver controls for open-collector emulation

   ----------------------------------------------------------------------------

   Sda_T <= '0' when ((master_slave = '1' and arb_lost = '0'

                       and sda_cout_reg = '0')

                       or (master_slave = '0' and slave_sda = '0')

                       or stop_scl_reg = '1') else

            '1';

   Sda_O <= '0';

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-09-2019

Re: axi iic ip example ties scl_o and sda_o to ground in the synthesized schematic

Hi,

Can you please share the AXI IIC IP configuration which you are using while creating design.

Regards,

Venu

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Observer
Observer
297 Views
Registered: ‎02-01-2018

Re: axi iic ip example ties scl_o and sda_o to ground in the synthesized schematic

Thank you for your reply.

The IP configuration is in picture.  I changed axi clock from 250Mhz to 100Mhz today, but no use.

image.png

 PS: The FPGA in my design is xcvu9p-flga2104-2-i.

 

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Visitor
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Registered: ‎03-27-2019

Re: axi iic ip example ties scl_o and sda_o to ground in the synthesized schematic

Hi.  Has anyone at Xilinx been able to confirm that sda_o and scl_o are grounded?  I just used 2018.2 to create the IIC example design and the schematic still shows the grounding of the two signals, just as with 2019.1. 

It doesn't seem like this should be so difficult.  Either I'm making a mistake in my creation of the example design or there is an actual problem with the generated code.  This is going on a month and a half with no resolution.

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-09-2019

Re: axi iic ip example ties scl_o and sda_o to ground in the synthesized schematic

Hi,

There is no change in the IP. Make sure that pull-up should be added to the external SDA/SCL lines accordingly.

Once the IP bitstream got generated, please program bistream and try to run existing example IIC project from SDK.

If you are still facing the same problem please upload your project for verification purpose.

Regards,

Venu

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Visitor
Visitor
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Registered: ‎03-27-2019

Re: axi iic ip example ties scl_o and sda_o to ground in the synthesized schematic

Hi, Venu.  I will try your suggestion tomorrow when I'm back in the lab.  In the meantime, have you tried creating the example and looking at the schematic?  Do you see the same grounding of the two signal lines?  If so, why would the code work at all?  (BTW, I've tried the example using both the KU3P and KU5P chip, 900 pin -2 versions)

Having you confirm or fail to confirm what I'm seeing would be helpful.

Best Regards. 

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Visitor
Visitor
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Registered: ‎03-27-2019

Re: axi iic ip example ties scl_o and sda_o to ground in the synthesized schematic

I tried the example design in the hardware and the scl and sda both function properly.  The schematic still shows both scl_o and sda_o grounded.  I guess it's better not to ask why...

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