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Observer
Observer
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Registered: ‎02-14-2018

bank0_ctrl0 (IOU_SLCR) Register Description

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In UG1087 Zynq UltraScale+ MPSoC Register Reference:

 

Together with the bank0_ctrl1 [drive1] bit field, controls the output drive strength of MIO pins [0:25].
Drive table for [drive0], [drive1]:
00 = 2 mA
01 = 4 mA
10 = 8 mA
11 = 12 mA

 

So would drive0=1, drive1=0 be 8 mA?  This is confusing since the "drivex" bits are named backwards from the usual convention of 0 being the right most bit.  Also the description should read "[drive0] : [drive1]".

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-25-2010

回复: bank0_ctrl0 (IOU_SLCR) Register Description

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Hi @cmuhlbauer,

 

Yes, x means bank number.

 

Thank

Simon

Thanks
Simon
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Xilinx Employee
Xilinx Employee
616 Views
Registered: ‎08-25-2010

回复: bank0_ctrl0 (IOU_SLCR) Register Description

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Hi @cmuhlbauer,

 

Yes, x means bank number.

 

Thank

Simon

Thanks
Simon
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