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Participant herwinchan
Participant
1,044 Views
Registered: ‎04-05-2013

bsp generation error for axi_interrupt in cascade mode

 I'm working on updating a microblaze based design in Vivado 2015.4.  The design grows the number of required interrupts to 38 (above 32).  So I implemented a cascaded interrupt controller design as seen in the attached file.  (The process was also explained in detail in PG099).  

 

I was able to build the image without errors.  However, after exporting to SDK and using the SDK tool to generate the BSP it seems that the files generated incorrectly.  See attached file (intc_cascade_xparameters.png).  From looking at the generated xparameters.h file, it seems that the system ignored intc_1 and did not generate any code for it.  It also seems to think that intc_0 is not in master mode. 

 

The actual drivers look like they support cascading interrupt controllers, however, it seems that the tools do not recognize this and does not generate the correct definitions.  Can someone confirm that this is an issue?  What is the recommended workaround?

intc_cascade_bd.png
intc_cascade_xparameters.png
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6 Replies
Moderator
Moderator
980 Views
Registered: ‎09-12-2007

Re: bsp generation error for axi_interrupt in cascade mode

Yes, this is a known issue is older versions of vivado. Is there a reason you are using 2015.4?
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Participant herwinchan
Participant
970 Views
Registered: ‎04-05-2013

Re: bsp generation error for axi_interrupt in cascade mode

I was not able to find the release notes on this issue.

Which version of Vivado has this problem been fixed for?

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Participant herwinchan
Participant
896 Views
Registered: ‎04-05-2013

Re: bsp generation error for axi_interrupt in cascade mode

I tried the same design in Vivado 2018.1 and have very similar results.

 

In the xparameters.h file generated, both interrupt blocks are defined as being in Normal mode:

 

From xparameters.h:

/* Canonical definitions for peripheral UBLAZE_AXI_INTC_0 */
#define XPAR_INTC_0_DEVICE_ID XPAR_UBLAZE_AXI_INTC_0_DEVICE_ID
#define XPAR_INTC_0_BASEADDR 0x41200000
#define XPAR_INTC_0_HIGHADDR 0x4120FFFF
#define XPAR_INTC_0_KIND_OF_INTR 0x00000000
#define XPAR_INTC_0_HAS_FAST 0
#define XPAR_INTC_0_IVAR_RESET_VALUE 0x00000010
#define XPAR_INTC_0_NUM_INTR_INPUTS 31
#define XPAR_INTC_0_INTC_TYPE 0

/* Canonical definitions for peripheral UBLAZE_AXI_INTC_1 */
#define XPAR_INTC_1_DEVICE_ID XPAR_UBLAZE_AXI_INTC_1_DEVICE_ID
#define XPAR_INTC_1_BASEADDR 0x41210000
#define XPAR_INTC_1_HIGHADDR 0x4121FFFF
#define XPAR_INTC_1_KIND_OF_INTR 0xFFFFFF00
#define XPAR_INTC_1_HAS_FAST 0
#define XPAR_INTC_1_IVAR_RESET_VALUE 0x00000010
#define XPAR_INTC_1_NUM_INTR_INPUTS 8
#define XPAR_INTC_1_INTC_TYPE 0

 

from xintc.h:

#define XIN_INTC_NOCASCADE 0 /* Normal - No Cascade Mode */
#define XIN_INTC_PRIMARY 1 /* Master/Primary controller */
#define XIN_INTC_SECONDARY 2 /* Secondary Slave Controllers */
#define XIN_INTC_LAST 3 /* Last Slave Controller */

 

The exported packet seems to be generated correctly.  I unzipped the .hdf file and took a peek at ublaze.hwh (I assume this is the file used to generate the bsp):

<PARAMETER NAME="C_EN_CASCADE_MODE" VALUE="1"/>
<PARAMETER NAME="C_CASCADE_MASTER" VALUE="1"/>
<PARAMETER NAME="Component_Name" VALUE="ublaze_axi_intc_0_0"/>

 

<PARAMETER NAME="C_EN_CASCADE_MODE" VALUE="0"/>
<PARAMETER NAME="C_CASCADE_MASTER" VALUE="0"/>
<PARAMETER NAME="Component_Name" VALUE="ublaze_axi_intc_1_0"/>

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Explorer
Explorer
395 Views
Registered: ‎04-22-2015

Re: bsp generation error for axi_interrupt in cascade mode

Anyone have any hints on this?  I'm running into the same problem with 2018.2.

Thanks, 

ken

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Moderator
Moderator
356 Views
Registered: ‎09-12-2007

Re: bsp generation error for axi_interrupt in cascade mode

I thought this was fixed. Can you add your HDF ill take a look, and create a patch if needed

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Explorer
Explorer
344 Views
Registered: ‎04-22-2015

Re: bsp generation error for axi_interrupt in cascade mode

Hi Stephen,

Unfortunately I can't share my .hdf here[*].  However I did find a workaround.

First, I applied the patch from AR#71300, which fixed the TYPE values but the interrupt numbering still restarted on each interrupt controller.

After poring through the tcl code and seeing what changed in that patch, I went back and changed the cascade to use the intr[31] input (via concat block) rather than the cascade_interrupt port, and change the 2nd interrupt controller (non-master) to use the single-pin interrupt output rather than the bussed interface output (I do not use fast interrupts).  That worked, I got both the TYPE values and interrupt numbering correct even without the driver patch from the AR.

(I should note though I have not yet tested it in hardware, that will change by tomorrow).

It would be nice to go back to using the interrupt interface inputs, as I'd like to offer my software developers the option of using fast interrupts.  But this will work for the time being at least.

Thanks,

ken

------------

[*] Here is a snippet of write_bd_tcl showing the interrupt controller arrangement in the version that does NOT produce the correct result:

# Create instance: cpu_0_intc_0, and set properties
set cpu_0_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 cpu_0_intc_0 ]
set_property -dict [ list \
CONFIG.C_ASYNC_INTR {0x02800000} \
CONFIG.C_CASCADE_MASTER {1} \
CONFIG.C_EN_CASCADE_MODE {1} \
CONFIG.C_HAS_FAST {0} \
CONFIG.C_HAS_ILR {0} \
CONFIG.C_IRQ_CONNECTION {0} \
CONFIG.C_KIND_OF_EDGE {0xFFFFFFFF} \
CONFIG.C_KIND_OF_INTR {0x00000001} \
CONFIG.C_KIND_OF_LVL {0xffffffdf} \
CONFIG.C_NUM_SW_INTR {0} \
] $cpu_0_intc_0

# Create instance: cpu_0_intc_1, and set properties
set cpu_0_intc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 cpu_0_intc_1 ]
set_property -dict [ list \
CONFIG.C_ASYNC_INTR {0x00000000} \
CONFIG.C_EN_CASCADE_MODE {0} \
CONFIG.C_KIND_OF_EDGE {0xFFFFFFFF} \
CONFIG.C_KIND_OF_INTR {0x00000001} \
CONFIG.C_KIND_OF_LVL {0xFFFFFFFF} \
CONFIG.C_NUM_SW_INTR {0} \
] $cpu_0_intc_1

# Create instance: intr_concat_0, and set properties
set intr_concat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 intr_concat_0 ]
set_property -dict [ list \
CONFIG.IN0_WIDTH {1} \
CONFIG.IN10_WIDTH {1} \
CONFIG.IN11_WIDTH {1} \
CONFIG.IN12_WIDTH {1} \
CONFIG.IN13_WIDTH {1} \
CONFIG.IN14_WIDTH {1} \
CONFIG.IN15_WIDTH {1} \
CONFIG.IN16_WIDTH {1} \
CONFIG.IN17_WIDTH {1} \
CONFIG.IN18_WIDTH {1} \
CONFIG.IN19_WIDTH {1} \
CONFIG.IN1_WIDTH {1} \
CONFIG.IN20_WIDTH {1} \
CONFIG.IN21_WIDTH {1} \
CONFIG.IN22_WIDTH {1} \
CONFIG.IN23_WIDTH {1} \
CONFIG.IN24_WIDTH {1} \
CONFIG.IN25_WIDTH {1} \
CONFIG.IN26_WIDTH {1} \
CONFIG.IN27_WIDTH {1} \
CONFIG.IN28_WIDTH {1} \
CONFIG.IN29_WIDTH {1} \
CONFIG.IN2_WIDTH {1} \
CONFIG.IN30_WIDTH {1} \
CONFIG.IN3_WIDTH {1} \
CONFIG.IN4_WIDTH {1} \
CONFIG.IN5_WIDTH {1} \
CONFIG.IN6_WIDTH {1} \
CONFIG.IN7_WIDTH {1} \
CONFIG.IN8_WIDTH {1} \
CONFIG.IN9_WIDTH {1} \
CONFIG.NUM_PORTS {31} \
] $intr_concat_0

# Create instance: intr_concat_1, and set properties
set intr_concat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 intr_concat_1 ]
set_property -dict [ list \
CONFIG.NUM_PORTS {32} \
] $intr_concat_1

connect_bd_intf_net -intf_net cpu_0_intc_1_interrupt [get_bd_intf_pins cpu_0_intc_0/cascade_interrupt] [get_bd_intf_pins cpu_0_intc_1/interrupt]
connect_bd_intf_net -intf_net microblaze_0_interrupt [get_bd_intf_pins interrupt] [get_bd_intf_pins cpu_0_intc_0/interrupt]
connect_bd_net -net intr_concat_0 [get_bd_pins cpu_0_intc_0/intr] [get_bd_pins intr_concat_0/dout]
connect_bd_net -net intr_concat_1 [get_bd_pins cpu_0_intc_1/intr] [get_bd_pins intr_concat_1/dout]

------------------------------------

Here is the modified snippet that DOES work:

# Create instance: cpu_0_intc_0, and set properties
set cpu_0_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 cpu_0_intc_0 ]
set_property -dict [ list \
CONFIG.C_ASYNC_INTR {0x02800000} \
CONFIG.C_CASCADE_MASTER {1} \
CONFIG.C_EN_CASCADE_MODE {1} \
CONFIG.C_HAS_FAST {0} \
CONFIG.C_HAS_ILR {0} \
CONFIG.C_IRQ_CONNECTION {0} \
CONFIG.C_KIND_OF_EDGE {0xFFFFFFFF} \
CONFIG.C_KIND_OF_INTR {0x00000001} \
CONFIG.C_KIND_OF_LVL {0xffffffdf} \
CONFIG.C_NUM_SW_INTR {0} \
] $cpu_0_intc_0

# Create instance: cpu_0_intc_1, and set properties
set cpu_0_intc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 cpu_0_intc_1 ]
set_property -dict [ list \
CONFIG.C_ASYNC_INTR {0x00000000} \
CONFIG.C_EN_CASCADE_MODE {0} \
CONFIG.C_IRQ_CONNECTION {1} \
CONFIG.C_KIND_OF_EDGE {0xFFFFFFFF} \
CONFIG.C_KIND_OF_INTR {0x00000001} \
CONFIG.C_KIND_OF_LVL {0xFFFFFFFF} \
CONFIG.C_NUM_SW_INTR {0} \
] $cpu_0_intc_1

# Create instance: intr_concat_0, and set properties
set intr_concat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 intr_concat_0 ]
set_property -dict [ list \
CONFIG.IN0_WIDTH {1} \
CONFIG.IN10_WIDTH {1} \
CONFIG.IN11_WIDTH {1} \
CONFIG.IN12_WIDTH {1} \
CONFIG.IN13_WIDTH {1} \
CONFIG.IN14_WIDTH {1} \
CONFIG.IN15_WIDTH {1} \
CONFIG.IN16_WIDTH {1} \
CONFIG.IN17_WIDTH {1} \
CONFIG.IN18_WIDTH {1} \
CONFIG.IN19_WIDTH {1} \
CONFIG.IN1_WIDTH {1} \
CONFIG.IN20_WIDTH {1} \
CONFIG.IN21_WIDTH {1} \
CONFIG.IN22_WIDTH {1} \
CONFIG.IN23_WIDTH {1} \
CONFIG.IN24_WIDTH {1} \
CONFIG.IN25_WIDTH {1} \
CONFIG.IN26_WIDTH {1} \
CONFIG.IN27_WIDTH {1} \
CONFIG.IN28_WIDTH {1} \
CONFIG.IN29_WIDTH {1} \
CONFIG.IN2_WIDTH {1} \
CONFIG.IN30_WIDTH {1} \
CONFIG.IN3_WIDTH {1} \
CONFIG.IN4_WIDTH {1} \
CONFIG.IN5_WIDTH {1} \
CONFIG.IN6_WIDTH {1} \
CONFIG.IN7_WIDTH {1} \
CONFIG.IN8_WIDTH {1} \
CONFIG.IN9_WIDTH {1} \
CONFIG.NUM_PORTS {32} \
] $intr_concat_0

# Create instance: intr_concat_1, and set properties
set intr_concat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 intr_concat_1 ]
set_property -dict [ list \
CONFIG.NUM_PORTS {32} \
] $intr_concat_1

connect_bd_intf_net -intf_net microblaze_0_interrupt [get_bd_intf_pins interrupt] [get_bd_intf_pins cpu_0_intc_0/interrupt]
connect_bd_net -net intc_0_concat [get_bd_pins cpu_0_intc_0/intr] [get_bd_pins intr_concat_0/dout]
connect_bd_net -net intc_1_cascade [get_bd_pins cpu_0_intc_1/irq] [get_bd_pins intr_concat_0/In31]
connect_bd_net -net intc_1_concat [get_bd_pins cpu_0_intc_1/intr] [get_bd_pins intr_concat_1/dout]

 

 

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