UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor sandy3129
Visitor
2,228 Views
Registered: ‎10-18-2014

can we connect axi gpio to axi traff gen start stop bits

1) can we connect axi gpio signals which is on the slave side to the axi traffic gen start, stop bits, which is on the master side of the axi interconnect, how can we do it??, since my axi gpios width cannot be a single bit which can be given to the axi traffic gen start stop bits.

2)I want to enable my axi traffic gen, on start bit from the axi gpio and write the data into the axi register which is on the slave side??

kindly help me I'm beginner to vivado model based design. i have build design as per the image attached on addition to this, i want to add the above features to it as well.

Regards

Sandeep

 

vivado.jpg

0 Kudos
1 Reply
Moderator
Moderator
2,189 Views
Registered: ‎07-31-2012

Re: can we connect axi gpio to axi traff gen start stop bits

Hi,

 

You can configure the width of AXI GPIO IP and then expand the port to connect specific GPIO output port to traffic generator.

 

Regards

Praveen


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos