UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer deepakddn
Observer
1,637 Views
Registered: ‎05-12-2016

clock wizard output and AXI 1G/2.5G Ethernet subsystem gtx_clk connection incompatinbility

I am using zcu102 eval board for my design. The board has 300 MHz input clock. When I use Zynq and MIG auto connection wizard with DDR4, the ZynQ ip gives a clock of 99.999 MHz instead of 100 MHz.  I use this clock to feed a clock wizard to generate 200 MHz and 125 MHz clocks to feed REF CLK and GTX CLK of AXI 1G/2.5G Ethernet subsystem (7.1) IP. As the clocks are not exact, these are shown as 198.xxx MHz and 124.xxx MHz ,respectively. However   AXI 1G/2.5G Ethernet subsystem (7.1) IP has clock period for gtx clock set to 8 ns in its IP generics settings.

When I run validate design, it gives me following message:

[BD 41-238] Port/Pin property FREQ_HZ does not match between /axi_ethernet_0/gtx_clk(125000000) and /axi_ethernet_0_refclk/clk_out2(124998750)

 

I am not sure how to remove this error. I tied to manually modify the pin property for Frequency in ip file config_mpsoc_axi_ethernet_0_0.v as:

(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.gtx_clk, FREQ_HZ 124998750, PHASE 0, CLK_DOMAIN /axi_ethernet_0_refclk_clk_out1" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.gtx_clk CLK" *)
input wire gtx_clk;

However, config_mpsoc_axi_ethernet_0_0_ooc.xdc file has period setting as: 

create_clock           -name gtx_clk              -period 8.000 [get_ports gtx_clk]

 

Please help me to remove this error. else let me know what is best to set up  ethernet IP connection on board.

 

Thanks

 

 

0 Kudos
5 Replies
Xilinx Employee
Xilinx Employee
1,620 Views
Registered: ‎08-01-2008

Re: clock wizard output and AXI 1G/2.5G Ethernet subsystem gtx_clk connection incompatinbility

try solution provided in this forum post
https://forums.xilinx.com/t5/Synthesis/Vivado-Synthesis-Error-BD-41-237-Bus-Interface-property-FREQ-HZ/td-p/462296
https://forums.xilinx.com/t5/Embedded-Processor-System-Design/BD-41-237-Bus-Interface-property-FREQ-HZ-does-not-match/td-p/412349
https://forums.xilinx.com/t5/Welcome-Join/How-can-I-change-the-FREQ-HZ-parameter-in-Vivado-2014-4-Thanks/td-p/592090
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Observer deepakddn
Observer
1,586 Views
Registered: ‎05-12-2016

Re: clock wizard output and AXI 1G/2.5G Ethernet subsystem gtx_clk connection incompatinbility

The problem is two fold:

1] The zcu102 board uses 300 MHz system clock. The DDR4 MIG finds the configuration for 100 MHz clock based on its M/D/D0 etc settings that is close to 100 Mhz but not exact. So, the freq is 99.99 MHz. I am using this frequency for system bus, which is also input to clocking wizard. Thus, for GTX, the closest output freq is 124.99875 MHz

 

2] The GTX clock of AXI 1G/2.5G Ethernet subsystem, is not configurable and is only read only param. This is always 125 MHz as I explained earlier. I could change AXI clock on this IP to be 99.99 MHz, but that did not help.

 

I am really stuck at this point . Is there a reference example design for this board to set up ethernet? I am using Vivado 2017.3 edition.

 

Thanks.

Deepak 

0 Kudos
Scholar jg_bds
Scholar
1,518 Views
Registered: ‎02-01-2013

Re: clock wizard output and AXI 1G/2.5G Ethernet subsystem gtx_clk connection incompatinbility

@deepakddn :

 

The clocking wizard in the DDR MIG works from the end, backwards.  It takes an expected memory-interface operating frequency, and tells you what reference clock you need for that.  It's not ideal to do what you're trying to do.

 

Generate your Ethernet GTX clock from the PS.  I believe the PS reference clock frequency is 33.333... MHz, so the PLL's running off this reference clock can get really close to the necessary operating frequencies, that a precise clock like 125.000 MHz can be generated.  (125-MHz is also a nice speed at which to run AXI's.)

 

-Joe G.

 

P.S.  I'm not sure what mode you're running it in, but the reference clock for the AXI Ethernet on a ZCU102 should probably NOT be 200-MHz.   

 

deepak-2.jpg

 

 

0 Kudos
Visitor dangtai1
Visitor
1,012 Views
Registered: ‎08-10-2017

Re: clock wizard output and AXI 1G/2.5G Ethernet subsystem gtx_clk connection incompatinbility

Hello,

Have you find a solution to this problem. I'm migrating my design from Vivado 2016.4 to Vivado 2018.2 and I get exactly the same problem... PL fabric clock targeted to 100MHz has a real value of 99.999MHz and this prevents me to generate the block design due to erros in clock wizards and GMII to RGMII IP
0 Kudos
Visitor dnr1406
Visitor
388 Views
Registered: ‎04-02-2019

Re: clock wizard output and AXI 1G/2.5G Ethernet subsystem gtx_clk connection incompatinbility

Don't know if this is still relevant but I encountered the same problem where the clock frequencies weren't precise enough for the AIi Ethernet subsystem to accept them. All I did is go to the Zynq MPSoC Configuration in Vivado -> go to clocking -> Input reference frequency and a couple of 3's to the input frequency behind the comma. This makes the output frequencies more precise and will eventually round up to an exact clock frequency.

Cheers,

 

Delano

0 Kudos