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Contributor
Contributor
326 Views
Registered: ‎05-31-2018

ddr3 design not working for component layout, but works for sodimm

Hi all,

I am using a custom design based on the board and design parameters given here:

http://warpproject.org/trac/wiki/HardwareUsersGuides/WARPv3/Memory

This is a 2gb sodimm memory part.

I am taking this reference IP and using it for a custom board, which has a slightly different ddr3 memory chip, but still compatible with the board. My issue is, however, that for some reason, reading and writing to the ddr3 is producing errors, namely, byte modification and byte nulling. 

For instance, a 32 bit write of 0x20D14C02 to 0xC0000016: will yield     0x00004C02, nulling the first two bytes. This happens in a pattern across difference Microblaze memory values during the memory test, for example, to 0xC0000006, or 0xC61A8006, etc. Not all addresses fail, and some fail for only 8 bit read/writes, or 64 bit read/writes, etc.

Does anyone have any idea as to why this most likely is? I was thinking maybe the MIG ip generator produces different parameters for a component design rather than an sodimm design, but looking through both options, I could not find any differences.

Does it look more like perhaps a trace length or a data strobe/clock synchronization issue? Any insights would be greatly appreciated! 

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2 Replies
Voyager
Voyager
278 Views
Registered: ‎02-01-2013

Re: ddr3 design not working for component layout, but works for sodimm

 

From your explanation, I gather you've got a custom board, with a custom DDR layout using component devices, and you've generated a MIG based on parameters that are for a loosely related DIMM. And it's not working.

The MIG doesn't "produce... parameters" for a particular DDR setup. You provide the parameters to the MIG, and it operates the controller based on those parameters--parameters like the ones in this GUI box:

2019-01-19_21-57-46.jpg

You need to compare the parameters that the MIG was generated against, with those in the component DDR's data sheet, and then adjust the MIG settings if they're different.

We can discuss trace length and routing issues if nothing improves after you make the changes above. (Hint: the next suggestion will be to slow down your memory clock to its slowest possible speed, to see if that helps.)

-Joe G.

 

 

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Scholar watari
Scholar
270 Views
Registered: ‎06-16-2013

Re: ddr3 design not working for component layout, but works for sodimm

Hi @az23

 

It seems preamble issue.

So, I recommend to make sure how to deal with Vref.

 

Would you make sure it ?

 

Best regards,

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