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Contributor
Contributor
895 Views
Registered: ‎04-06-2018

device tree for 2 DMA

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Hi, I've instantiated a DMA in my Zynq project with Linux and it is working fine. Now my module needs a second DMA to read and write different data from the memory, these two DMAs will communicate with the same module inside the FPGA using AXIS (but right now is all loop back).

When I edit my device tree just replicating the first one and changing the address I get a panic message from Kernel :

Unhandled fault: imprecise external abort (0x406) at 0x00000000

Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007

 

\0x14CPU1: stopping

\0x14CPU: 1 PID: 0 Comm: swapper/1 Not tainted 3.15.0-xilinx #1

@h\0xc5\0x1a\0xc1013f00>] (unwind_backtrace) from [<c0010570>] (show_stack+0x10/0x14)

P[<c0010570>] (show_stack) from [<c04ec2a0>] (dump_stack+0x88/0xd8)

([<c04ec2a0>] (dump_stack) from [<c0012810>] (ipi_cpu_stop+0x3c/0x6c)

\0x14[<c0012810>] (ipi_cpu_stop) from [<c0012eac>] (handle_IPI+0x60/0x80)

\0x14[<c0012eac>] (handle_IPI) from [<c00084e0>] (gic_handle_irq+0x54/0x5c)

([<c00084e0>] (gic_handle_irq) from [<c0010f80>] (__irq_svc+0x40/0x70)

\0x14Exception stack(0xe6c8bf68 to 0xe6c8bfb0)

\0x14bf60: e6c8bfb0 00000004 fcfe7cca 00000000 e71a10e0 00000000

\0x14bf80: fcba6ca3 00000000 c0727e98 413fc090 c0727e98 00000000 00000000 e6c8bfb0

\0x14bfa0: c005d248 c03a2058 60000113 ffffffff

([<c0010f80>] (__irq_svc) from [<c03a2058>] (cpuidle_enter_state+0x50/0xe8)

([<c03a2058>] (cpuidle_enter_state) from [<c004d50c>] (cpu_startup_entry+0x14c/0x1c0)

\0x14[<c004d50c>] (cpu_startup_entry) from [<00008584>] (0x8584)

\0x14---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007

 

 

my original and working device tree address is

axi_dma_0: axi_dma_0@40400000 {
            axistream-connected = <&axi_dma_0>;
                    axistream-control-connected = <&axi_dma_0>;
            #dma-cells = <1>;
            clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
            clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>, <&clkc 15>;
            compatible = "xlnx,axi-dma","xlnx,axi-dma-1.00.a","xlnx,axi-dma-6.03.a";
            interrupt-names = "mm2s_introut", "s2mm_introut";
            interrupt-parent = <&intc>;
            interrupts = <0 33 4 0 34 4>;
            xlnx,enable-multi-channel = <0x0>;
            xlnx,family = "zynq";
                xlnx,generic = <0x0>;
            xlnx,include-mm2s = <0x1>;
            xlnx,include-mm2s-dre = <0x1>;
            xlnx,include-mm2s-sf = <0x1>;
            xlnx,include-s2mm = <0x1>;
            xlnx,include-s2mm-dre = <0x1>;
            xlnx,include-s2mm-sf = <0x1>;
            xlnx,instance = "axi_dma_0";
            xlnx,mm2s-burst-size = <16>;
            xlnx,s2mm-burst-size = <16>;
            reg = <0x40400000 0x10000>;
            //xlnx,include-sg;
            xlnx,addrwidth = <64>;
            //xlnx,sg-length-width = <64>;
            dma-channel@40400000 {
                compatible = "xlnx,axi-dma-mm2s-channel";
                dma-channels = <0x1>;
                interrupts = <0 33 4>;
                xlnx,datawidth = <64>;
                xlnx,device-id = <0x0>;
            };
            dma-channel@40400030 {
                compatible = "xlnx,axi-dma-s2mm-channel";
                dma-channels = <0x1>;
                interrupts = <0 34 4>;
                xlnx,datawidth = <64>;
                xlnx,device-id = <0x1>;
            };
        };

axidmatest_1: axidmatest@1 {
                     compatible ="xlnx,axi-dma-test-1.00.a";
                     dmas = <&axi_dma_0 0
                             &axi_dma_0 1>;
                     dma-names = "axidma0", "axidma1";
        };

 

which I just duplicated for :

axi_dma_1: axi_dma_1@40410000 {
            axistream-connected = <&axi_dma_1>;
                    axistream-control-connected = <&axi_dma_1>;
            #dma-cells = <1>;
            clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
            clocks = <&clkc 15>, <&clkc 15>, <&clkc 15>, <&clkc 15>;
            compatible = "xlnx,axi-dma","xlnx,axi-dma-1.00.a","xlnx,axi-dma-6.03.a";
            interrupt-names = "mm2s_introut", "s2mm_introut";
            interrupt-parent = <&intc>;
            interrupts = <0 35 4 0 36 4>;
            xlnx,enable-multi-channel = <0x0>;
            xlnx,family = "zynq";
                xlnx,generic = <0x0>;
            xlnx,include-mm2s = <0x1>;
            xlnx,include-mm2s-dre = <0x1>;
            xlnx,include-mm2s-sf = <0x1>;
            xlnx,include-s2mm = <0x1>;
            xlnx,include-s2mm-dre = <0x1>;
            xlnx,include-s2mm-sf = <0x1>;
            xlnx,instance = "axi_dma_0";
            xlnx,mm2s-burst-size = <16>;
            xlnx,s2mm-burst-size = <16>;
            reg = <0x40410000 0x10000>;
            //xlnx,include-sg;
            xlnx,addrwidth = <64>;
            //xlnx,sg-length-width = <64>;
            dma-channel@40410000 {
                compatible = "xlnx,axi-dma-mm2s-channel";
                dma-channels = <0x1>;
                interrupts = <0 35 4>;
                xlnx,datawidth = <64>;
                xlnx,device-id = <0x2>;
            };
            dma-channel@40410030 {
                compatible = "xlnx,axi-dma-s2mm-channel";
                dma-channels = <0x1>;
                interrupts = <0 36 4>;
                xlnx,datawidth = <64>;
                xlnx,device-id = <0x3>;
            };
        };

axidmatest_2: axidmatest@2 {
                     compatible ="xlnx,axi-dma-test-1.00.a";
                     dmas = <&axi_dma_1 0
                             &axi_dma_1 1>;
                     dma-names = "axidma2", "axidma3";
        };

 

A FURTHER question is :

is it better if the use a new second HP at Zynq , HP1 and  for my second DMA ?

Screenshot from 2018-11-27 13-29-49.png
Screenshot from 2018-11-27 13-39-51.png
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1 Solution

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Contributor
Contributor
825 Views
Registered: ‎04-06-2018

Re: device tree for 2 DMA

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I solved it with two GP and HP , then it created all address right and worked with Linux and my driver that uses DMA registers.

No problems at dmesg and all dmas detected :

cat /proc/interrupts

63:          0          0       GIC  63  gpio1
 64:          0          0       GIC  64  gpio2
 65:          0          0       GIC  65  xilinx-dma-controller
 66:          0          0       GIC  66  xilinx-dma-controller
 67:          0          0       GIC  67  xilinx-dma-controller
 68:          0          0       GIC  68  xilinx-dma-controller

 

cat /proc/iomem

00000000-2fffffff : System RAM
00008000-006b9587 : Kernel code
006ee000-00763323 : Kernel data
40400000-4040ffff : /amba/axi_dma_0@40400000
80400000-8040ffff : /amba/axi_dma_1@80400000

 

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2 Replies
Contributor
Contributor
826 Views
Registered: ‎04-06-2018

Re: device tree for 2 DMA

Jump to solution

I solved it with two GP and HP , then it created all address right and worked with Linux and my driver that uses DMA registers.

No problems at dmesg and all dmas detected :

cat /proc/interrupts

63:          0          0       GIC  63  gpio1
 64:          0          0       GIC  64  gpio2
 65:          0          0       GIC  65  xilinx-dma-controller
 66:          0          0       GIC  66  xilinx-dma-controller
 67:          0          0       GIC  67  xilinx-dma-controller
 68:          0          0       GIC  68  xilinx-dma-controller

 

cat /proc/iomem

00000000-2fffffff : System RAM
00008000-006b9587 : Kernel code
006ee000-00763323 : Kernel data
40400000-4040ffff : /amba/axi_dma_0@40400000
80400000-8040ffff : /amba/axi_dma_1@80400000

 

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580 Views
Registered: ‎02-26-2019

Re: device tree for 2 DMA

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Hi, I am testing two dmas and I have met a question is that how to modify the device and the dma driver source code . According to your way to modifing the device tree I wonder how to modify the driver source code ? My source code is from github https://github.com/bperez77/xilinx_axidma/tree/master/driver , can you give me some suggestions ? Thank you very much.

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