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Visitor vk8583
Visitor
337 Views
Registered: ‎03-18-2019

extending AXI memory mapped interface to CPLD from FPGA running microblaze

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hi,

    Can anyone suggest best way to extend MM interface to CPLD. I have a artix 7 FPGA running microblaze and it is connected to CPLD through IO lines. I would like to read/write registers in CPLD through memory mapped interface from Artix-7 FPGA . Can anyone suggest a suitable method for this?

regards,

vishal k

 

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Xilinx Employee
Xilinx Employee
293 Views
Registered: ‎01-09-2019

Re: extending AXI memory mapped interface to CPLD from FPGA running microblaze

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Hello @vk8583 

Have you tried looking at AXI Chip2Chip?  This is the normal solution for FPGA <=> FPGA connections, but you may also be able to use it for FPGA <=> CPLD.  I am not sure what type of CPLD this is so am not sure if you will be able to implement the Chip2Chip IP on that side.

AXI Chip2Chip Product Guide: https://www.xilinx.com/support/documentation/ip_documentation/axi_chip2chip/v5_0/pg067-axi-chip2chip.pdf

If you just want to communicate over AXI and have the pins, you could try implementing all the pins for the AXI interface (this will be pin intensive so is not recommended).  This may work depending on your design scenario.  It might be worth looking into the AXI4-Lite interface if you want to go this direction as the pin requirements would be greatly reduced.

Finally what is driving the use of a CPLD as opposed to a low-cost alternative FPGA?  If your design could use an FPGA in the same class as the CPLD that could make the design process easier.

Thanks,
Caleb
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3 Replies
Xilinx Employee
Xilinx Employee
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Registered: ‎01-09-2019

Re: extending AXI memory mapped interface to CPLD from FPGA running microblaze

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Hello @vk8583 

Have you tried looking at AXI Chip2Chip?  This is the normal solution for FPGA <=> FPGA connections, but you may also be able to use it for FPGA <=> CPLD.  I am not sure what type of CPLD this is so am not sure if you will be able to implement the Chip2Chip IP on that side.

AXI Chip2Chip Product Guide: https://www.xilinx.com/support/documentation/ip_documentation/axi_chip2chip/v5_0/pg067-axi-chip2chip.pdf

If you just want to communicate over AXI and have the pins, you could try implementing all the pins for the AXI interface (this will be pin intensive so is not recommended).  This may work depending on your design scenario.  It might be worth looking into the AXI4-Lite interface if you want to go this direction as the pin requirements would be greatly reduced.

Finally what is driving the use of a CPLD as opposed to a low-cost alternative FPGA?  If your design could use an FPGA in the same class as the CPLD that could make the design process easier.

Thanks,
Caleb
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Visitor vk8583
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270 Views
Registered: ‎03-18-2019

Re: extending AXI memory mapped interface to CPLD from FPGA running microblaze

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Thanks Caleb,

                       AXI Chip2Chip is not an option since selected CPLD doesnt support it. Due to cost constraint CPLD is selected as an IO extender.So the only workaround solution would be to use AXI4-lite customize it and use accordingly. If any other option is available please let me know.

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-09-2019

Re: extending AXI memory mapped interface to CPLD from FPGA running microblaze

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@vk8583 

The only other thing you could look into would be to look at using the Aurora (maybe 8b/10b) phy for the transmitting/receiving off-chip.  https://www.xilinx.com/support/documentation/ip_documentation/aurora_8b10b/v11_1/pg046-aurora-8b10b.pdf

Would that be viable in your application and with your devices?

Thanks,
Caleb
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