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Scholar ronnywebers
Scholar
6,699 Views
Registered: ‎10-10-2014

flush an AXI4-Stream Data FIFO

Hello,

 

I'm looking for the best way to flush an AXI4-Stream data fifo.

 

So far my best solution is to use an AXI GPIO pin, and hard-reset the IP block. I've 'AND-ed' this with the 'peripheral_aresetn' line from the Processor System Reset.

 

Is there another way to do this? Can I use the fifo generator to generate an AXI4-Stream Data fifo, with some AXI4-Lite accessible control registers, so that it can be done through software instead?

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