UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
4,553 Views
Registered: ‎01-14-2014

fsync_in & fsync_out[n : 0] in Video timing Controller IP

Jump to solution

Hi,

I am facing problem in driving fsync in signal in VTC ip.

what signal from Video in to axi out ip will drive this signal and what this signal signify.

and same how to utilize fsync_out and why it has some width.

what is it signify.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
5,908 Views
Registered: ‎07-11-2011

Re: fsync_in & fsync_out[n : 0] in Video timing Controller IP

Jump to solution

Hi,

 

Assuming high period of fsync_out  signifies frame start, its hight time can be used as synchronization signal to susequent modules.

For the display device it has some internal functions like the raster has to trace back from right bottom pixel to left top pixel.

Assume it as a reset with some pulse width.

 

det_aclken and gen_aclken are inputs to VTC,  they are  clock enables for detector and geneator clocks.

You can drive them externally or can tie them to logic high always. 

 

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
5 Replies
Xilinx Employee
Xilinx Employee
4,551 Views
Registered: ‎07-11-2011

Re: fsync_in & fsync_out[n : 0] in Video timing Controller IP

Jump to solution

Hi,

 

Fsync signifies frame start.

It has some width based on your configuration, however you will not receive any data in its deactive period.

Note that fsync has polarity as well, please do google search for frame start signal details.

PG043  figure 3-5 will show you teh connectivity of VTC , AXI blocks

 

http://www.xilinx.com/support/documentation/ip_documentation/v_vid_in_axi4s/v3_0/pg043_v_vid_in_axi4s.pdf

 

 

Regards,

Vanitha.

 

 

 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
Xilinx Employee
Xilinx Employee
4,546 Views
Registered: ‎07-11-2011

Re: fsync_in & fsync_out[n : 0] in Video timing Controller IP

Jump to solution

Hi,

 

If you are new to Video designs i would suggest you to go through UGs in teh below link and pick one of the reference design so that it gives you a good start.

 

http://www.xilinx.com/esp/video/refdes_listing.htm

 

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
Adventurer
Adventurer
4,543 Views
Registered: ‎01-14-2014

Re: fsync_in & fsync_out[n : 0] in Video timing Controller IP

Jump to solution

 

Thanks for your valuable support.Please clear some more doubts about these signals

 

And one more doubt in this.

why fsync_out if i say it show frame start for axi4in to video out ip, then what its width signifies.

i searched it about this but i didnt got solution for this,

and det_aclken and gen_aclken are dependent on other signals or must be provided externally, and how to control these enable signals .

0 Kudos
Adventurer
Adventurer
4,540 Views
Registered: ‎01-14-2014

Re: fsync_in & fsync_out[n : 0] in Video timing Controller IP

Jump to solution

yes i am also seeing these ugs.

but some doubts being arise and making problem in design, doubts may be silly.

but thanks for your support.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
5,909 Views
Registered: ‎07-11-2011

Re: fsync_in & fsync_out[n : 0] in Video timing Controller IP

Jump to solution

Hi,

 

Assuming high period of fsync_out  signifies frame start, its hight time can be used as synchronization signal to susequent modules.

For the display device it has some internal functions like the raster has to trace back from right bottom pixel to left top pixel.

Assume it as a reset with some pulse width.

 

det_aclken and gen_aclken are inputs to VTC,  they are  clock enables for detector and geneator clocks.

You can drive them externally or can tie them to logic high always. 

 

 

Regards,

Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented