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Visitor sandy3129
Visitor
1,928 Views
Registered: ‎10-18-2014

how can i convert my transaction from external pins to axi full transaction?

hello friends, how can we create a axi full transaction from external pins(single pins) in vivado environment, I have 128 bit data pin, 32 bit address pin and single bit wr_en pin, how do i create a axi full transaction from these pins, so that i can store the data received from the external pins into AXI Block RAM's.

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3 Replies
Scholar hbucher
Scholar
1,913 Views
Registered: ‎03-22-2016

Re: how can i convert my transaction from external pins to axi full transaction?

@sandy3129 Not sure this is the answer you look for but on Vivado Tools/Create and Package new IP  wizard will create an AXI full (or AXI LITE) interface and wrapper for you to customize. Then you just plugin your current IP inside. 

Tutorial:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug1119-vivado-creating-packaging-ip-tutorial.pdf

Video tutorial:

https://www.xilinx.com/video/hardware/packaging-custom-ip-integrator.html

 

 

 

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Visitor sandy3129
Visitor
1,860 Views
Registered: ‎10-18-2014

Re: how can i convert my transaction from external pins to axi full transaction?

yes, but im having a 128 bit to be stored into the brams, transacting from a custom master ip( created using  axi full master) peripheral with  128 bit wdata is not posssible, each 128 bit should be divided into 4 32 bit words, and must be stored in the brams , even if i can do the slicing of the 128 bit word peripheral inside the ip, im having issues with the full axi peripheral controls, if i connect the custom master ip directly to brams its working but if i connect zynq to read the data , the transactions are stopping at the axi peripheral itself, not going through bram controller and brams.

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Xilinx Employee
Xilinx Employee
1,846 Views
Registered: ‎02-01-2008

Re: how can i convert my transaction from external pins to axi full transaction?

If I understand what you are after, there are a few ways to do this.

 

You could include the axi bram controller in the BD and connect its BRAM_PORTA to an outgoing interface port and place the bram outside of the BD. But you will have to manage the bram, how data bits are mux'd etc.

 

Maybe the easiest way is place the axi bram controller and block memory generator in the BD. But connect BRAM_PORTB from the block memory generator to an outgoing port. In this case, you change the bram generator from mode=bramController to standalone, make sure 'generate address interface with 32bits' is enabled, and make sure Port A output registers are disabled.

 

More specifics for the second method:

  • You will get a critical warning that can be ignored 'CRITICAL WARNING: [BD 41-237] Bus Interface property MASTER_TYPE does not match between /dp_bram/BRAM_PORTA(OTHER) and /axi_bram_ctrl_0/BRAM_PORTA(BRAM_CTRL)'
  • I have attached a design example that uses the VIO core to write to the 128bit BRAM_PORTB. I have all 16bits of write enable connected to the VIO but in your case, you can probably tie them together

1.png

2.png

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4.png

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