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Adventurer
Adventurer
2,509 Views
Registered: ‎07-10-2015

how to export zynq xps settings in Vivado2016.4?

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I know how to import.but how to export?

 

import xps.png
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Teacher muzaffer
Teacher
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Registered: ‎03-31-2012

Re: how to export zynq xps settings in Vivado2016.4?

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@christine1225 xml file comes from an xps export. Basically the flow is you generate a configuration in xps in the gui and then you can export this configuration and import it to another project etc.

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Teacher muzaffer
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Registered: ‎03-31-2012

Re: how to export zynq xps settings in Vivado2016.4?

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@christine1225 I don't think Vivado has an export facility to create xml files for xps to read.

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Adventurer
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Registered: ‎07-10-2015

Re: how to export zynq xps settings in Vivado2016.4?

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Thank you.

 

If I want to import xps settings, do I need to write the xml on my own myself? 

 

where does the xml file come from?

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Teacher muzaffer
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Registered: ‎03-31-2012

Re: how to export zynq xps settings in Vivado2016.4?

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@christine1225 xml file comes from an xps export. Basically the flow is you generate a configuration in xps in the gui and then you can export this configuration and import it to another project etc.

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Participant michaeltymcnamara
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Registered: ‎07-08-2013

Re: how to export zynq xps settings in Vivado2016.4?

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I have not been able to obtain any useful effect by using Import XPS Settings, or the other work arounds posted in this forum.

What has worked for me for the task of capturing the IP customization settings for the Zynq processing system IP (and really for any of the IPs), from one design in a manner where you could re-apply these to a later design, is the following:

Do

File -> Export -> Export Hardware

Pick a directory, for symplicty, choose Local to Project

In the project directory on disk, if your design is called design_1, find the file design_1.sdk/design_wrapper.hdf

Alternatively, if your hardware team has given you an exported hardware file, import this into SDK.  If the design was called "design_1" (which is the default name) then open the directory design_1_wrapper_hw_platform_0.

In that directory will be a file called system.hdf

This file is actually a zip file, open it using gzip or 7z

File the file design_bd.tcl in that zip file, or xxxx_bd.tcl if the design is called xxxx

Open the file, and for the Zynq settings. search for processing_system7

Observe tcl code that looks like the below.    The section "set_property -dict [ list " through to the end is the golden nugget.

# Create instance: sys_ps7, and set properties
set sys_ps7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7 ]
set_property -dict [ list \
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
...
CONFIG.PCW_WDT_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
CONFIG.PCW_WDT_WDT_IO.VALUE_SRC {DEFAULT} \
] $sys_ps7

 

Copy this statement into a file, called say, zynq_settings.tcl, and then change the $sys_ps7 at the end to

[get_bd_cells processing_system7_0]

 

Your file will look like the below (except the '...' will have many lines setting up many things)

set_property -dict [ list \
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
...
CONFIG.PCW_WDT_PERIPHERAL_ENABLE.VALUE_SRC {DEFAULT} \
CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ.VALUE_SRC {DEFAULT} \
CONFIG.PCW_WDT_WDT_IO.VALUE_SRC {DEFAULT} \
] [get_bd_cells processing_system7_0]

Now create a new design in Vivado

Create an instance of the Zynq processor

( Add IP, type zynq, and select the one that shows up)

Then type source zynq_settings.tcl

in the tcl window, and these settings will be imported.

You will likely get some errors like:

CRITICAL WARNING: [BD 41-1276] Cannot set the parameter PCW_SINGLE_QSPI_DATA_MODE on /processing_system7_0. Parameter does not exist

as the design you are building does not have the QSPI selected yet.

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