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Visitor aznshodan
Registered: ‎09-15-2015

how to get peak throughput for AXI DMA

Currently I am trying to stream image data from Processing System and we are getting around 100MB/s of throughput. On the datasheet it says you can get around 300MB/s of throughput using AXI DMA. 

I tried the following:

1. use max burst size in DMA

2. change the PL clock to 150MHz

3. use 23bit buffer length register


Even though I did this, i get around 130MB/s of throughput. 

I am sending the data through an hls module that i made called grayscale. it is combinational - it takes 32bit value in and outputs the grayscale value (which is just adding up red green blue and dividing it by 3). 


How do i get the max bandwidth?



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2 Replies
Teacher muzaffer
Registered: ‎03-31-2012

Re: how to get peak throughput for AXI DMA

so you are reading from hp0 and writing to hp1 port (?) is the 130 MB/s the sum of these two transfers or one side only? One thing you can try is to connect one of the masters to hp2 as hp0/1 share a ddr port and hp2/3 share another so the combination of hp0+hp2 might give you better performance.
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Xilinx Employee
Xilinx Employee
Registered: ‎08-02-2011

Re: how to get peak throughput for AXI DMA

Yeah, it could be any number of things. I'd do some probing and make use of AXI Performance monitors, timers, profiling, etc to help narrow down where the bottleneck is. The DMA setup may or may not be the issue.


One thing to consider is that SG mode will allow you to queue BDs. Meaning your SW can work on setting up the next transfer while the DMA is working on the current transfer. This will eliminate downtime that you have when using simple mode when the SW receives an interrupt indicating a transfer is done and then has to set up the next transfer. This adds some complexity, though, so I'd only do it after said investigation and you're sure this is the most significant limiting factor.

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