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Observer mohamd17
Observer
2,963 Views
Registered: ‎01-14-2017

how to set values in the same register in the PL side

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Hello
I have flags that I set from my PS soc. Know to read them from PL side I have an implementation error when I use the same register !

 

    test1 <= slv_reg3(31);
    test2 <= slv_reg3(30);
    PSenable <= slv_reg3(29);

Untitled.png

Thank you

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1 Solution

Accepted Solutions
Explorer
Explorer
5,429 Views
Registered: ‎10-05-2010

Re: how to set values in the same register in the PL side

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@mohamd17 wrote:

yes but this is done on purpose.

How to write several times on the same register and avoid this error ?
 
	en_ram_wr <= slv_reg3(31);
	en_ram_rd <= slv_reg3(30);
	PSenable <= slv_reg3(29);

Use the OR gate. For example, in Verilog:
 
@always @(posedge clock)
  if (writeEnable1) slv_reg <= data1;
  else if (writeEnable2) slv_reg <= data2;
 
Make sure that all signals are synchronous to clock.
 
---
Joe Samson
 

 

View solution in original post

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5 Replies
Scholar dpaul24
Scholar
2,947 Views
Registered: ‎08-07-2014

Re: how to set values in the same register in the PL side

Jump to solution

Hi,

 

It is showing a multi driver problem, it is having 2 drivers.

 

slv_reg3(31) bit is being driven from en_ram_wr_reg/Q and slv_reg3_reg[31]/Q. Check your connections to slv_reg3(31) and fix it.

 

Regards.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
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Observer mohamd17
Observer
2,941 Views
Registered: ‎01-14-2017

Re: how to set values in the same register in the PL side

Jump to solution

yes but this is done on purpose.

How to write several times on the same register and avoid this error ?
 
	en_ram_wr <= slv_reg3(31);
	en_ram_rd <= slv_reg3(30);
	PSenable <= slv_reg3(29);
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Explorer
Explorer
5,430 Views
Registered: ‎10-05-2010

Re: how to set values in the same register in the PL side

Jump to solution

@mohamd17 wrote:

yes but this is done on purpose.

How to write several times on the same register and avoid this error ?
 
	en_ram_wr <= slv_reg3(31);
	en_ram_rd <= slv_reg3(30);
	PSenable <= slv_reg3(29);

Use the OR gate. For example, in Verilog:
 
@always @(posedge clock)
  if (writeEnable1) slv_reg <= data1;
  else if (writeEnable2) slv_reg <= data2;
 
Make sure that all signals are synchronous to clock.
 
---
Joe Samson
 

 

View solution in original post

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Scholar dpaul24
Scholar
2,917 Views
Registered: ‎08-07-2014

Re: how to set values in the same register in the PL side

Jump to solution

yes but this is done on purpose.

How to write several times on the same register and avoid this error ?
 
The above OR gate example is perhaps the simplest.
 
I don't know your design so I am speculating. Say for e.g. if 3 signals have to change a bit (which is a register), then you should have a MUX whose select lines would govern which signal will change the bit value. You can't connect all the 3 signals to this bit. It would generate a multi-driven condition as you have now.
 
Ans yes, for registers this change should happen at the rising edge of the clock.
--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
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Observer mohamd17
Observer
2,915 Views
Registered: ‎01-14-2017

Re: how to set values in the same register in the PL side

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thank you, I translated that into VHDL and it works.
It was necessary to make a condition on each bit of the register, this allows to write and read on the same register several times.
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