UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer binbinyantai
Observer
376 Views
Registered: ‎09-12-2017

how to understand the problems in Zynq-7000 AP SoC Boot - Locking and Executing out of L2 Cache Tech Tip

hi

 i want to lock some critical code into l2 cache ,i find the tech tip in the network, but i can not understand the tech tip, i  find the tech tip lock the whole application into the l2 cache .which is not what i want . i just want to lock the isr routine ,not all the application code . but i do not know how to do that

 

i think i did not understand the tech tip well ,because i think i am not familiar with something

 

as follows is in the tech tip ,but i think it is wrong

 

FSBL Software flow for preloading application to L2 cache and locking it:

  • Set page table entry attribute to “No Inner cacheable and No Outer cacheable” for OCM memory region used for FSBL. In the reference example FSBL runs from OCM memory, range 0x00000000 - 0x30000000
  • Set page table entry attribute to “Inner and outer cacheable” , for FLASH linear memory region used for Application code segments loading address. In the reference example Applications use linear FLASH memory, range 0xfc700000 - 0xfdffffff set to Outer
  • Cacheable but not Inner cacheable.

question 1: range 0x00000000 - 0x30000000?  is it wrong?

 

question 2 : 

  • 0xfc700000 - 0xfdffffff set to Outer
  • Cacheable but not Inner cacheable.

this two lines should be in the same line? but the two lines separate from each other , is it wrong ?

 

 

 

 

 

0 Kudos