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Newbie russmoning
Newbie
6,732 Views
Registered: ‎09-18-2015

implementing multiple external peripheral interfaces

 I am looking to access multiple external devices thru the AXI interface on a Zynq device.  Looking at the EPC this seems to be the correct IP for the job but in the example from the documentation there is this magic block labeled External Glue Logic.  Can anyone direct me to some example/description of how to put the data bus back together.  I would think that if this is the intneded method of interfacing external peripherals the bus interface could be reconstructed by the IP.

 

 

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Xilinx Employee
Xilinx Employee
6,723 Views
Registered: ‎08-01-2008

Re: implementing multiple external peripheral interfaces

http://www.xilinx.com/products/intellectual-property/axi_epc.html
Thanks and Regards
Balkrishan
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Teacher drjohnsmith
Teacher
6,719 Views
Registered: ‎07-09-2009

Re: implementing multiple external peripheral interfaces

external glue logic !

 

belive it or not, that is not a get out, 

 

So ,

 

inside the FPGA signals are always uni directional, and always '1' or '0'.

 

In your picture, for instance, you see 

prh_data_i , this is the 16 bits of data comming in from the outside world to the fpga.

prh_data_o, this is the 16 bots of data going out of the fpga to the outside world.

prh_data_t, this is telling the outside world that data is comming into our out fo the fpga.

 

Now your logic won't run on '1' and '0' it will need voltages .

 

So the glue logic is the I/O interface of the FPGA, specifying for instance the logic type, and drive level

 

You could also have a bi directional data bus outside the FPGA.

   Then you _i and _o and _t go to a tri state buffer in the FPGA IO, and the _t turns the IO on at the right time.

 

in vhdl it would be something like

 

prh_data_o <= <my data_out > when prh_data_t = '1' else ( others => 'Z' );

and prh_data_i is the signal comming in.

 

Hop this helps, 

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