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Visitor frosteyes
Visitor
5,618 Views
Registered: ‎11-16-2009

map bram interface out of xps design

I have a problem with mapping a lmb bram interface out from xps. The lmb_bram_if_cntlr ip core in XPS has changed its design rule check. In lmb_bram_if_cntlr_v2_10_a it generated a warning if a bram was not connected, now it generate an error.

 

DRC from lmb_bram_if_cntlr_v2_10_a
if {[string length $busif] == 0} {
  puts "WARNING: $instname memory controller is not connected to a bram block"
}


DRC from lmb_bram_if_cntlr_v2_10_b
if {[bus_is_connected $mhsinst "BRAM_PORT"] == 0} {
  error "The BRAM_PORT interface is not correctly connected. To use the interface the bus must be connected to a BRAM." "" "mdt_error"
} else {
  set busif [xget_value $mhsinst "bus_interface" "BRAM_PORT"]
  if {[string length $busif] == 0} {
    puts "WARNING: $instname memory controller is not connected to a bram block"
  }
}


In the change log it is also noted by the following statement:


11.3 - Changes in Tcl script files associated with core (.tcl)
  Added DRC to check that BRAM_PORT interface is connected [CR<521127>].

 

As the old version only generated a warning, it was possible to create an external interface by adding the ports to the mhs file. See the next section. If the ports is made external, they can be mapped to some BRAM outside the XPS. If one trying this with the new version, platgen generate the DRC error.

 

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = lmb_bram_if_cntlr_0
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00020000
 PARAMETER C_HIGHADDR = 0x0002ffff
 BUS_INTERFACE SLMB = dlmb
 PORT BRAM_Dout_A = lmb_bram_if_cntlr_0_BRAM_Dout_A
 PORT BRAM_Din_A = lmb_bram_if_cntlr_0_BRAM_Din_A
 PORT BRAM_Addr_A = lmb_bram_if_cntlr_0_BRAM_Addr_A
 PORT BRAM_WEN_A = lmb_bram_if_cntlr_0_BRAM_WEN_A
 PORT BRAM_EN_A = lmb_bram_if_cntlr_0_BRAM_EN_A
 PORT BRAM_Clk_A = lmb_bram_if_cntlr_0_BRAM_Clk_A
 PORT LMB_Clk = sys_clk_s
 PORT LMB_Rst = sys_rst_s
END

 

Is there anybody who knows where I can get more info based on the number in the change log? If someone has an idea for how to map the controller out of XPS, in an easy way I would like to know it very much.

 

Im thinking on making a kind of custom wrapper ip core?

 

Thanks ahead.

Message Edited by frosteyes on 11-16-2009 01:35 PM
Tags (4)
3 Replies
Visitor frosteyes
Visitor
5,606 Views
Registered: ‎11-16-2009

Re: map bram interface out of xps design

Solved by creating the following IP

 

 

------------------------------------------------------------------------------------------- -- -- Modulename : BRAM wrapper -- Filename : bram_wrapper.tex -- Date : 16 Nov 2009 -- Programmer : Claus Stovgaard, CST, claus@frosteyes.dk -- General -- Description : Small wrapper module for the bus interface from a bram -- controller inside the xps, to a interface there can be mapped to external -- ports. -- -- Comment : -- History : Rev. Date Init. Remark -- 1 16 Nov 2009 CST Init release -- ------------------------------------------------------------------------------------------- -- -- Copyright (c) 2009, Claus Stovgaard - claus@frosteyes.dk -- All rights reserved. -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions are met: -- * Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- * Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- * Neither the name of the project (Ethernet Powerlink - Made Easy) nor the -- names of its contributors may be used to endorse or promote products -- derived from this software without specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY Claus Stovgaard - claus@frosteyes.dk ''AS IS'' AND ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -- DISCLAIMED. IN NO EVENT SHALL Claus Stovgaard BE LIABLE FOR ANY -- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity bram_wrapper is generic ( C_LMB_AWIDTH : integer := 32; C_LMB_DWIDTH : integer := 32 ); port ( -- ports to BRAM bus IN_BRAM_Rst_A : in std_logic; IN_BRAM_Clk_A : in std_logic; IN_BRAM_Addr_A : in std_logic_vector(0 to C_LMB_AWIDTH-1); IN_BRAM_EN_A : in std_logic; IN_BRAM_WEN_A : in std_logic_vector(0 to C_LMB_DWIDTH/8-1); IN_BRAM_Dout_A : in std_logic_vector(0 to C_LMB_DWIDTH-1); IN_BRAM_Din_A : out std_logic_vector(0 to C_LMB_DWIDTH-1); -- ports to external interface BRAM_Rst_A : out std_logic; BRAM_Clk_A : out std_logic; BRAM_Addr_A : out std_logic_vector(0 to C_LMB_AWIDTH-1); BRAM_EN_A : out std_logic; BRAM_WEN_A : out std_logic_vector(0 to C_LMB_DWIDTH/8-1); BRAM_Dout_A : out std_logic_vector(0 to C_LMB_DWIDTH-1); BRAM_Din_A : in std_logic_vector(0 to C_LMB_DWIDTH-1) ); end entity bram_wrapper; architecture imp of bram_wrapper is ------------------------------------------------------------------------------------------- -- component declarations ------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------- -- internal signals ------------------------------------------------------------------------------------------- begin -- architecture IMP BRAM_Rst_A <= IN_BRAM_Rst_A; BRAM_Clk_A <= IN_BRAM_Clk_A; BRAM_Addr_A <= IN_BRAM_Addr_A; BRAM_EN_A <= IN_BRAM_EN_A; BRAM_WEN_A <= IN_BRAM_WEN_A; BRAM_Dout_A <= IN_BRAM_Dout_A; IN_BRAM_Din_A <= BRAM_Din_A; end architecture imp;

 And the mpd file

 

 

################################################################### ## ## Name : bram_wrapper ## Desc : Microprocessor Peripheral Description ## : Automatically generated by PsfUtility ## ################################################################### BEGIN bram_wrapper ## Peripheral Options OPTION IPTYPE = PERIPHERAL OPTION IMP_NETLIST = TRUE OPTION DESC = BRAM Wrapper OPTION LONG_DESC = Allows the Block RAM interface to be mapped out external OPTION ARCH_SUPPORT_MAP = (aspartan3=PREFERRED, spartan3=PREFERRED, spartan3an=PREFERRED, spartan3a=PREFERRED, spartan3e=PREFERRED, spartan3adsp=PREFERRED, virtex4lx=PREFERRED, virtex4sx=PREFERRED, virtex4fx=PREFERRED, virtex5lx=PREFERRED, virtex5sx=PREFERRED, virtex5fx=PREFERRED, aspartan3e=PREFERRED, aspartan3a=PREFERRED, aspartan3adsp=PREFERRED, qvirtex4lx=PREFERRED, qvirtex4sx=PREFERRED, qvirtex4fx=PREFERRED, qrvirtex4lx=PREFERRED, qrvirtex4sx=PREFERRED, qrvirtex4fx=PREFERRED, spartan6t=EARLY_ACCESS, spartan6=EARLY_ACCESS, virtex6lx=EARLY_ACCESS, virtex6sx=EARLY_ACCESS, virtex6cx=EARLY_ACCESS) OPTION HDL = VHDL OPTION STYLE = HDL OPTION IP_GROUP = ETHERNET Powerlink - Made Easy ## Bus Interfaces BUS_INTERFACE BUS = BRAM_PORT, BUS_STD = XIL_BRAM, BUS_TYPE = TARGET ## Generics for VHDL or Parameters for Verilog PARAMETER C_LMB_AWIDTH = 32, DT = INTEGER PARAMETER C_LMB_DWIDTH = 32, DT = INTEGER ## Ports PORT IN_BRAM_Rst_A = BRAM_Rst, DIR = I, BUS = BRAM_PORT PORT IN_BRAM_Clk_A = BRAM_Clk, DIR = I, BUS = BRAM_PORT PORT IN_BRAM_Addr_A = BRAM_Addr, DIR = I, VEC = [0:(C_LMB_AWIDTH-1)], BUS = BRAM_PORT PORT IN_BRAM_EN_A = BRAM_EN, DIR = I, BUS = BRAM_PORT PORT IN_BRAM_WEN_A = BRAM_WEN, DIR = I, VEC = [0:((C_LMB_DWIDTH/8)-1)], BUS = BRAM_PORT PORT IN_BRAM_Dout_A = BRAM_Dout, DIR = I, VEC = [0:(C_LMB_DWIDTH-1)], BUS = BRAM_PORT PORT IN_BRAM_Din_A = BRAM_Din, DIR = O, VEC = [0:(C_LMB_DWIDTH-1)], BUS = BRAM_PORT PORT BRAM_Rst_A = "", DIR = O PORT BRAM_Clk_A = "", DIR = O PORT BRAM_Addr_A = "", DIR = O, VEC = [0:(C_LMB_AWIDTH-1)] PORT BRAM_EN_A = "", DIR = O PORT BRAM_WEN_A = "", DIR = O, VEC = [0:((C_LMB_DWIDTH/8)-1)] PORT BRAM_Dout_A = "", DIR = O, VEC = [0:(C_LMB_DWIDTH-1)] PORT BRAM_Din_A = "", DIR = I, VEC = [0:(C_LMB_DWIDTH-1)] END

 

 

 This solve the problem

 

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Observer seanhong
Observer
4,008 Views
Registered: ‎11-15-2010

Re: map bram interface out of xps design

could you give a further idea on how to create this new IP, with these two files?

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Visitor frosteyes
Visitor
3,994 Views
Registered: ‎11-16-2009

Re: map bram interface out of xps design

In your XPS folder create, a pcores/bram_wrapper_v1_00_a/ folder

 

The pcores folder is for your private cores. bram_wrapper_v1_00_a is the name for the folder.

 

In this bram wrapper folder - create a data folder and a hdl/vhdl folder.

 

So you have the vhdl file in:

 

 XPS / pcores / bram_wrapper_v1_00_a / hdl / vhdl / bram_wrapper.vhd

 

And in the data folder

 

XPS / pcores / bram_wrapper_v1_00_a / data / bram_wrapper_v2_1_0.mpd

XPS / pcores / bram_wrapper_v1_00_a / data / bram_wrapper_v2_1_0.pao

 

See the Xilinx documentation regarding private IP cores for further information

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