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Explorer
Explorer
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Registered: ‎05-01-2017

more than 64 emio pins of zynq ?

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Hi Xilinx,

                vivado/sdk 2017.4, xc7z020clg400-2 custom board

I have a custom board with 80+ pinout.

in vivado block diagram, I selected spi0 / spi1 / uart0 as EMIO, and assigned pinout in constrain file accordingly. Then, to my surprise, I still can select  extra 64 EMIO gpios, and assign pinout. Vivado generates bitstream successfully.

It seems I got more than 64 EMIO pins of xc7z020clg400.

Please help to clarify. Thanks in advance.

Mike

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Scholar jg_bds
Scholar
162 Views
Registered: ‎02-01-2013

Re: more than 64 emio pins of zynq ?

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Don't confuse MIO with EMIO. MIO are dedicated pins that can be allocated to PS memory interfaces and IO peripherals for direct connections to the outside of the chip.

Many peripheral signals that could be connected to MIO pins can also be re-directed to the PL, as EMIO signals, for use therein or for external chip connections using SelectIO resources within the PL.

2019-10-14_15-25-41.jpg

In addition, there are two, 32-bit banks of dedicated GPIO in the PS that are available for connection only to the PL:

2019-10-14_15-24-51.jpg

Enabling these 64 EMIO in the PS only makes them available to the PL. Whether or not you have IO resources within the PL to bring those signals outside the chip depends on your custom implementation.

-Joe G.

 

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Moderator
Moderator
236 Views
Registered: ‎09-12-2007

Re: more than 64 emio pins of zynq ?

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These are 64 GPIO pins between the PS and the PL.

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Highlighted
Scholar jg_bds
Scholar
163 Views
Registered: ‎02-01-2013

Re: more than 64 emio pins of zynq ?

Jump to solution

 

Don't confuse MIO with EMIO. MIO are dedicated pins that can be allocated to PS memory interfaces and IO peripherals for direct connections to the outside of the chip.

Many peripheral signals that could be connected to MIO pins can also be re-directed to the PL, as EMIO signals, for use therein or for external chip connections using SelectIO resources within the PL.

2019-10-14_15-25-41.jpg

In addition, there are two, 32-bit banks of dedicated GPIO in the PS that are available for connection only to the PL:

2019-10-14_15-24-51.jpg

Enabling these 64 EMIO in the PS only makes them available to the PL. Whether or not you have IO resources within the PL to bring those signals outside the chip depends on your custom implementation.

-Joe G.

 

View solution in original post

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