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Observer
Observer
1,021 Views
Registered: ‎08-28-2018

ports connection problem

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Hello here,

 

I'm currently using the clk_wiz IP in vivado(2018.2) to generate a clock signal and I want to output it to a GPIO pin on my board Ultra96. I made an external to a port named clk_out1_1. Then I can't find nothing to use about the clk_wiz. After that, I tried to write the code below in the constraint file.

set_property PACKAGE_PIN D10  [get_ports {clk_out1_1        }];  # "D10.MIO36_PS_GPIO1_0"

But I still get nothing from the pin D10. Just woundering how can I connect the output signal from an IP block to such as a GPIO pin? And do I need to initialize it in SDK code? Thanks!

 

Regards,

Han

 

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Observer
Observer
835 Views
Registered: ‎08-28-2018

Re: ports connection problem

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The problem is fixed. Just post to help anyone who have the same problem. The reset port of clk_wiz is auto-connected and it is set to high automatically which means the clk_wiz is reseting by itself. I banned the reset port on clk_wiz and it works good now.

View solution in original post

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Xilinx Employee
Xilinx Employee
971 Views
Registered: ‎10-30-2017

Re: ports connection problem

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Hi @pmuproject,

 

No need of the SDK here. when you properly route the signal to GPIO pin then it is expected to be out on that pin. 

are you giving proper input to the clocking wizard IP?

what is the status of the locked signal in clk_wiz?

 

Please check these things in your design.

 

Best Regards,
Srikanth
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Observer
Observer
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Registered: ‎08-28-2018

Re: ports connection problem

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Hi Srikanth,

 

Thanks for your reply! The input is the clock of the Zynq UltraSCALE+ CPU as shown in the figure below:

capture.PNG

Inside the clk_wiz, I used MMCM and the input clock frequency is 100MHz. The output frequency is 20MHz due to I need an output 20MHz to the GPIO pin. I wrote the code as below in contraints to route the output port to the GPIO pin HD_GPIO_0 which is a HD GPIO pin in PL.

set_property PACKAGE_PIN D7   [get_ports {clk_out1_1               }];  # "D7.HD_GPIO_0"

But I just can get a normal GPIO pin when I used ocilascope to measure the voltage. There are 2 things I want to ask:

1. Am I right to route the output signal correct by using the above code in constraint only?

2. How to use the GPIO in PL? I can't find the ID to write code in SDK. For example, the IDs of PS GPIO pins are defined in the xparameter.h file and I can use APIs to use them directly. But I can't find the IDs of the PL GPIO pins. 

Thanks!

 

Regards,

Han

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Xilinx Employee
Xilinx Employee
932 Views
Registered: ‎10-30-2017

Re: ports connection problem

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Hi @pmuproject,

 

I got it. Please follow below steps

 

create the BD as shown below:

clock_out.PNG

write the constraint for the clk_out1_0 (connect it to the PL pin).

 

Generate the bit file and export it to SDK with bit stream. create the FSBL application targeting a53.

program the bit stream and run the FSBL. observe the out put on the PL GPIO pin.

  

Best Regards,
Srikanth
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Observer
Observer
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Registered: ‎08-28-2018

Re: ports connection problem

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Hi @savula,

 

Thanks for your reply!

I followed your description but it doesn't work on my board. Could you please help me to chek my work procedure?

First I create the BD as below:

bd.PNG

Then the HDL wrapper is created. The constraint is connected to the pin F7 which is HD_GPIO2 on my board as shown:

constriant.PNG

Then the bitstream is generated. Export hardware includes Bitstream. Lanuch SDK. Then a new project is created as below:

newproject.PNG

Then FSBL project is selected. After building I pressed programm FPGA and selected the clocktest project then pressed run as -> launch on Hadrware. Then I used oscillosope to meaured the pin 7 which is HD_GPIO2 but there is nothing. Did I make any mistake?

 

Regards,

Han

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Xilinx Employee
Xilinx Employee
899 Views
Registered: ‎10-30-2017

Re: ports connection problem

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Hi @pmuproject,

 

Please use the ODDR clock forwarding technique.

 

Best Regards,
Srikanth
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Observer
Observer
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Registered: ‎08-28-2018

Re: ports connection problem

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Hi @savula,

 

Sorry I didn't get you. For ODDR do you mean the data is transimitting both rising and falling edge? For clock forwading I searched on Google but it doesn't make sense for me. And where can I implement it? Thanks!

 

Regards,

Han

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Observer
Observer
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Registered: ‎08-28-2018

Re: ports connection problem

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Hi @savula

 

I got what you mean! I added the ODDR as below:

oddr.PNG

And then I have connect the port clk_out_0 to package pin D7 which is my HD_GPIO_0(I'm using Ultra96 board). Then the bitstream is generated and launched SDK. Then the FSBL project is created and programmed FPGA and run the FSBL project. But I still get nothing on the GPIO pin...... Anything else I missed? Thanks for you help!

 

Regards,

Han

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Observer
Observer
836 Views
Registered: ‎08-28-2018

Re: ports connection problem

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The problem is fixed. Just post to help anyone who have the same problem. The reset port of clk_wiz is auto-connected and it is set to high automatically which means the clk_wiz is reseting by itself. I banned the reset port on clk_wiz and it works good now.

View solution in original post

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