cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer
Observer
5,965 Views
Registered: ‎04-19-2010

ppc440mc_ddr data errors

I am using MT16HTS51264HY-667A1 SODIMM DDR2 of 4GB size with PPC440 on Virtex5 FX70T, custom board which has the same pinout interface as ML507 Eval board.

 

system.mhs

BEGIN ppc440_virtex5

 PARAMETER INSTANCE = ppc440_0

 ....................

 PARAMETER C_PPC440MC_CONTROL = 0xF810008F

 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC

 PORT CPMINTERCONNECTCLK = clk_198_0000MHzPLL0

 PORT CPMMCCLK = clk_198_0000MHzPLL0_ADJUST

END


BEGIN ppc440mc_ddr2

 PARAMETER INSTANCE = ppc440mc_ddr2_0 

PARAMETER HW_VER = 3.00.b
 PARAMETER C_MEM_BASEADDR = 0x00000000
 PARAMETER C_MEM_HIGHADDR = 0xBFFFFFFF

 PARAMETER HW_VER = 3.00.b

 PARAMETER C_MEM_BASEADDR = 0x00000000

 PARAMETER C_MEM_HIGHADDR = 0xBFFFFFFF

 

 PARAMETER C_DDR_RAWIDTH = 15

 PARAMETER C_DDR_BAWIDTH = 3

 PARAMETER C_NUM_RANKS_MEM = 2

 PARAMETER C_NUM_IDELAYCTRL = 3

 PARAMETER C_DDR2_ODT_WIDTH = 2

 PARAMETER C_SIM_ONLY = 0

 PARAMETER C_IODELAY_GRP = ppc440mc_ddr2_0

 PARAMETER C_MC_MIBCLK_PERIOD_PS = 5050

 PARAMETER C_DDR_TRFC = 70000

 PARAMETER C_DDR_TREFI = 7800

 PARAMETER C_NUM_CLK_PAIRS = 2

 PARAMETER C_INCLUDE_ECC_SUPPORT = 0

 PARAMETER C_MIB_MC_CLOCK_RATIO = 0

 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC

 PORT mi_mcreset = sys_periph_reset

 PORT mc_mibclk = clk_198_0000MHzPLL0_ADJUST

 PORT mi_mcclk90 = clk_198_0000MHzPLL0_ADJUST_PHASE90

 PORT mi_mcclkdiv2 = clk_99_0000MHzPLL0_ADJUST

 PORT mi_mcclk_200 = clk_198_0000MHzPLL0_ADJUST    // this is known to be working earlier

 


.................pins..................


END

 

It fails memory test with simple pattern write/reads as below:

 

 

int memtests()

{

u32 addr = XPAR_PPC440MC_DDR2_0_MEM_BASEADDR + (1024 * 1024); // start at 1MB offset

u32 boundary = addr + ((1 * 1024) * 80); // check KBs


int errs = 0, nerrs = 0;

u32 i;


// access at burst lengths of 4 bytes


// write a pattern

for (i = addr; i < boundary; i+= 4) {

unsigned char* ptr = (unsigned char *) i;

*ptr = 0xA5;


if(*ptr != 0xA5)

errs++;

}


//NOTE: No errs as of here

errs = nerrs = 0;


// read a pattern

for (i = addr; i < boundary; i+= 4) {

unsigned char* ptr = (unsigned char*) i;

unsigned char aa = *ptr;

if(aa != 0xA5)

errs++;

else

nerrs++;

}


//NOTE: lots of errs here

return XST_SUCCESS;

}

 

 

 

I get lots of errors in the data. Any clues would be appreciated.

0 Kudos
7 Replies
Highlighted
Xilinx Employee
Xilinx Employee
5,951 Views
Registered: ‎07-30-2007

Re: ppc440mc_ddr data errors

What are your PPC440 MHS *_CONFLICT_MASK parameters?  Otherwise your MHS seems reasonable at a quick glance.

0 Kudos
Highlighted
Observer
Observer
5,938 Views
Registered: ‎04-19-2010

Re: ppc440mc_ddr data errors

 

PARAMETER C_PPC440MC_CONTROL = 0xF810008F
 PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x00FFFE00
 PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x07000000

 

Calulated using param: C_DDR_WIDTH(64), AO(3), Col.Addr Width(10), Row.Addr Width(15), BA Width(3)

 

PARAMETER C_PPC440MC_CONTROL = 0xF810008F

PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x00FFFE00

PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x07000000

 

Though this reduces the errors count, i still see a huge error rate with code similar to Xil_TestMem32(XIL_TESTMEM_FIXEDPATTERN)

 

Additional observation:

the errors occurs with increase in time between writes and reads.

i.e: write and read of 50KB without any delay has zero errors. Adding 10ms delay between write of 50KB and read back, it adds 4 errors. Similarly write/read of 1MB has lots of errors as the delay is introduced by loop writing more bytes.

And its always the first byte that flips in a DWORD. e.g: 0xDEADBEEF on error changes to 0x4EADBEEF

0 Kudos
Highlighted
Observer
Observer
5,912 Views
Registered: ‎04-19-2010

Re: ppc440mc_ddr data errors

Just identified that i missed the "DQS Read Postamble Glitch Squelch" constraints in UCF. :smileymad:

 

Will see if this resolves

0 Kudos
Highlighted
Observer
Observer
5,905 Views
Registered: ‎04-19-2010

Re: ppc440mc_ddr data errors

that additional constraints didn't make any difference at all

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
5,863 Views
Registered: ‎07-30-2007

Re: ppc440mc_ddr data errors

I would suggest checking your memory parameters against the memory vendor datasheet, especially TREFI.  After that, are your ODT and I/O STANDARD settings set as you intend?

Then, make sure your IOBs have registers packed into them by looking at Section 6 of the .mrp map report- you should see at least OFF1/2 in every output.

Highlighted
Visitor
Visitor
5,427 Views
Registered: ‎01-20-2011

Re: ppc440mc_ddr data errors

Hello,

I'm using xc5vfx30t -2ff665 ,have the same question, some body can help me?

0 Kudos
5,274 Views
Registered: ‎04-03-2008

Re: ppc440mc_ddr data errors

Hello,

 

I'm using xc5vfx100t -1ff1136 , have the same question, any updates?

0 Kudos