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Adventurer
Adventurer
11,019 Views
Registered: ‎06-05-2014

problem with TDATA widths in AXI4 Stream Broadcaster

In Vivado 2014.2 the AXI4 stream broadcaster seems to have a tdata width on the output that is twice what it should be. Is this correct or is it a bug?

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11 Replies
Xilinx Employee
Xilinx Employee
10,994 Views
Registered: ‎08-02-2011

Re: problem with TDATA widths in AXI4 Stream Broadcaster

Most IP Integrator IP will automatically infer data widths from the cores driving them and propagate that to the output types. Try hooking the core into your system and see if it still is the same.
www.xilinx.com
Newbie zhuang123
Newbie
10,590 Views
Registered: ‎01-13-2014

Re: problem with TDATA widths in AXI4 Stream Broadcaster

I met the same problem.

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Visitor geoffjones
Visitor
10,249 Views
Registered: ‎02-04-2014

Re: problem with TDATA widths in AXI4 Stream Broadcaster

 

Same problem. All of the output ports are twice the width that they should be.  I've tried leaving the settings on 'auto' and then hooking up the ports but they don't change. This is version 1.1 of the IP and I'm using Vivado 2014.2

 

broadcaster.png

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Adventurer
Adventurer
9,953 Views
Registered: ‎02-14-2014

Re: problem with TDATA widths in AXI4 Stream Broadcaster

I'm getting something similar.   Perhaps I've missed something but I can't see how this block is even supposed to work at all?

 

It's not just the outputs (m_axis drivers) that are doubled, it's the input too for m_axis_tready.   However the doubling on this tready signal (only) is accounted for inside the block - looking at the synthesis, the two m_axis tready signals are AND'ed together and used to drive the s_axis tready.  In other words the broadcaster block only signals upstream that's it's ready when all of it's children are ready, this part makes perfect sense.

 

But the tlast, tuser etc. are different.   Each of these signals comes in from s_axis as a single signal input. The outputs to m_axis however are vectors, the doubling mentioned, and I suspect is actually one bit per output m_axis port.  But:  each s_axis signal is just wired straight to the first bit (only) of the m_axis output, meaning that it connects to the first child m_axis block only!  See the blue highlighted signals in the screenshot attached.  The other bits in the vector are just optimised away and tied low, so nothing works.  

 

Can someone from Xilinx please step in and confirm how exactly this block is supposed to be used, perhaps an example or testbench?  The docs for this (in the AXI stream suite) or the similar AXI Video Broadcaster don't have any detail of what is supposed to happen with all these signals.

 

 Screenshot from 2015-04-15 11:16:44.png

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Explorer
Explorer
9,318 Views
Registered: ‎09-25-2014

Re: problem with TDATA widths in AXI4 Stream Broadcaster

Year and no answer... So Axi-Broadcaster is just "AND" for tready signal and thats all?
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9,221 Views
Registered: ‎03-27-2014

Re: problem with TDATA widths in AXI4 Stream Broadcaster

I realized that by checking the pin/interface properties in the block design:
consider S[15:0] => ( M[15:0] = M00, M[31:16]=M01 ), the 16 bit input is duplicated into one LSB/MSB 32 word, which appears as two interfaces /M00 and /M01.
G.W.,
NIST - Time Frequency metrology
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Adventurer
Adventurer
4,779 Views
Registered: ‎03-03-2010

Re: problem with TDATA widths in AXI4 Stream Broadcaster


@alexkarnaukhov wrote:
Year and no answer... So Axi-Broadcaster is just "AND" for tready signal and thats all?

No, it's not just that. The TVALIDs for each master also need to be adjusted. So its:

 

1) S_READY = M_READY_1 & M_READY_2

2) M_VALID_1 = S_VALID & M_READY_2

3) M_VALID_2 = S_VALID & M_READY_1

 

This deals with the case where one master is valid and the other isn't. Without #2 and #3 included, the valid master will see an asserted valid and an asserted ready, so it'll think it's a valid databeat. But it isn't, because the other master isn't ready. So it's necessary to drive the valid low when the opposite master isn't ready to deal with this case.

 

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Visitor me_sur
Visitor
2,305 Views
Registered: ‎02-16-2018

Re: problem with TDATA widths in AXI4 Stream Broadcaster

I encountered similar issues in 2017.4

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Voyager
Voyager
2,079 Views
Registered: ‎05-30-2017

Re: problem with TDATA widths in AXI4 Stream Broadcaster

Also in 2018.2

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Xilinx Employee
Xilinx Employee
1,796 Views
Registered: ‎02-01-2008

Re: problem with TDATA widths in AXI4 Stream Broadcaster

I have ran into slightly different issues regarding data width from the broadcaster. The simplest solution for me was to set the data width manually instead of relying on the 'auto' data width which uses parameter propagation to update the widths.

 

And my specific issue will also occur in 2018.3.

Highlighted
Visitor moons520
Visitor
307 Views
Registered: ‎07-30-2017

Re: problem with TDATA widths in AXI4 Stream Broadcaster

I have the same problem。I hope s_axis_tdata[31:0], m_axis_tdata[23:0].

how to set this ip?)ZS{C9IX`M1PQ3$W%RH~Z)P.pngE]1{V)XI4`Z_JP0@)LX{SOK.png

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