cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Newbie
Newbie
184 Views
Registered: ‎10-27-2019

question about axi4-stream data fifo width convertion

hi Experts,

     I have 16bit width high speed input data need to be stored into DDR, so I setup a path like:

selectio -> stream fifo -> dma -> ddr

    since the input clock is 200Mhz, it's 4x higher than the bus clock 50Mhz, I think:

    If I can use the 64bit width bus to read the fifo at 50Mhz to get the input data blance - ly?

    If the answer is yes, I can't found anywhere to set different data width of input/output on the stream fifo property setting dialog, otherwise I think I need anther IP to convert the width before the fifo:

无标题.png

    Even so, I found that the reading clock of the stream data fifo still needs 200Mhz clock rather than 50Mhz which I want.

    What I can do? or just leave everything there, it will work for me? Thanks a lot!

 

BR

Un1

0 Kudos