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Visitor sols
Registered: ‎01-21-2014

read after write and write after write hazards in Zynq/AXI BFM

In simulation, when write tp a certain address is sent through the HP1 port into the DDR/DRAM and immediately followed with a read to the same address before the write response is received, the read data is corrupt. The sequence of operations is like this:


1. Write address A with data D
2. Read address A (same address as above)
3. BFM sends write response
4. BFM sends read data which is not D


Some AXI documentation on ARM web-site has the following info:


"The AXI specification defines that RAW and WAR ordering is determined by the master, whereas RAR and WAW ordering is enforced by the slave. If an AXI master requires ordering between reads and writes to certain memory locations, it must wait for a write response before issuing a read from a location it has written to (RAW). It must also wait for read data before issuing a write to a location it has read from (WAR)."


Is this true for Zynq HP ports?


Do HP ports have write buffer(s) for RAW?


Is there any RTL (Verilogexample of master implementation that handles RAW and WAR ordering/hazards?



Also, when 2 single byte writes to the same word (but not to the same byte) are sent to HP port, x appears in BFM simulation. AXI spec implies that such case (WAW hazard) should be handled correctly by the slave. Is it true? Is it a bug in BFM?

1 Reply
Visitor kokoz
Registered: ‎01-17-2017

Re: read after write and write after write hazards in Zynq/AXI BFM

Really interesting topic.
Still no solution?

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