07-14-2019 11:58 PM
Till now I was doing AD9361 based reference design in KC705 board with DDR configuration. It was working fine
Now I want to implement AD9361 based design in custom board for Kintex-7 FPGA. It doesn't have DDR memory. So I removed memory interface generator and provided axi_clk input from sys_clk_p and sys_clk_n using clock wizard. I increased memory size of sys_dlmb_cntlr and sys_ilmb_cntlr to 1M. DisabledM_AXI_DC and M_AXI_IC ports in Microblaze block design. And compiled and exported design to SDK.
But I'm getting an error when I'm loading .elf file through SDK while testing in KC705 board.
An internal error occurred during: "Launching New_configuration". No Target with ID 0
Unexpected error while launching program.
java.lang.RuntimeException: Debug Operation Not Supported on the Target, Current Processor State is not "Stopped"
MicroBlaze Pipeline Stalled on a Blocking Instruction or Invalid Bus Access
Stalled PC: 0x00000000
Try Resetting the Processor to Continue..
What might be the possible reason? Anything else has to do while removing DDR memory from design.
Hoping for positive reply.
07-15-2019 03:19 AM
Hi @ipsita ,
I suspect that address is beginning of the DDR memory.
Try going into the linker script in SDK and running the program from the OCM RAM instead of the DDR.
07-15-2019 03:40 AM
Thanks for the reply.
Modified section to memory region mapping as sys_ilmb_cntlr_Mem_sys_dlmb_cntlr_Mem. Still issue is there.I increased the size of sys_ilmb_cntlr_Mem_sys_dlmb_cntlr_Mem to 0x100000. I have even edited address editor in vivado.
Please find the attached screenshots.
I have a doubt in linker script. Eventhough I removed ddr control and linear flash, why it is still showing as available memory region?.
07-16-2019 04:41 AM
After you implemented your new design, did you export it to the SDK? (File -> Export -> Export Hardware...)