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Explorer
Explorer
860 Views
Registered: ‎01-15-2008

strange Zynq ethernet response behavior

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I have a zedboard, "bare-metal" design using lwip 14.1.  Vivado 2016.2, SDK 2016.2.  

My design uses the Zync PS to move data to/from the EMAC0.  Sending and receiving UDP packets.

It all works, sort of, but sometimes it misses packets.  I understand that UDP is not guaranteed, but I need the speed. And it misses packets even when things are happening very slowly.

 

If I remove everything from my recv_callback() except the pbuf_free(), I can see that the ARP function is doing something funny: it takes two ARP requests from the host (usually 1 second apart)  to receive two ARP responses from the zed, following the second request:

Capture.PNG

For instance here at 57 seconds the host asks "Who's got 1.10?" and then the same exactly 1 second later.  Then two responses from the zed, just 1 microsecond apart

 

When I restore my recv_callback() to its desired function, the same is seen for UDP responses- often no response from the zed will be seen until the second UDP request from the host is sent, at which time two responses are seen.  As though data is being sucked up in a transmit FIFO somewhere.

 

I will greatly appreciate any ideas!

 

Thanks

 

Rick

 

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1 Solution

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Explorer
Explorer
1,118 Views
Registered: ‎01-15-2008

Re: strange Zynq ethernet response behavior

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Well, at some point I took a look at the SDK 2016.2 "Tasks"pane and I saw this

 

Capture2.PNG

Looks like maybe LWIP wasn't quite ready for prime time.

I saved a copy of the Vivado project, opened it in Vivado 2017.4.  I didn't recompile, but re-exported the hardware using the same bitstream (God knows the horrors of upgrading all of the IP cores).  Opened in SDK 2017.4, and all works perfectly

Rick

 

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3 Replies
Xilinx Employee
Xilinx Employee
827 Views
Registered: ‎04-03-2018

Re: strange Zynq ethernet response behavior

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Hi @rikraf,

 

In your project BSP settings check whether xilmfs is enabled along with lwip. And, also try to set in lwip BSP settings with below lwip customized parameters and see if there is any improvement or not. 

LWIP customized parameters

MEM_SIZE 524288
MEMP_NUM_PBUF 1024
MEMP_NUM_TCP_SEG 1024
PBUF_POOL_SIZE 8192
N_RX_DESCRIPTORS = 512
N_TX_DESCRIPTORS = 512
TCP_SND_BUF 65535
TCP_WND 65535
TCP_IP_TX_CHECKSUM_OFFLOAD= true
TCP_IP_RX_CHECKSUM_OFFLOAD= true

 

Please find attached screenshots of modifying BSP settings.

bsp-lwp.png
bsp-lwp-1.png
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Explorer
Explorer
818 Views
Registered: ‎01-15-2008

Re: strange Zynq ethernet response behavior

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Hello Drajunad,

Thanks for those suggestions.  I tried them, to no avail.

Can't see why I'd need xilmfs or large amounts of pbuf memory for this little bit of data transmission, but in any event, it didn't help.

I've also tried many other bsp settings, with no change in behavior.  It seems like something deep in the hardware...

 

But thanks for trying!

 

Rick

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Explorer
Explorer
1,119 Views
Registered: ‎01-15-2008

Re: strange Zynq ethernet response behavior

Jump to solution

Well, at some point I took a look at the SDK 2016.2 "Tasks"pane and I saw this

 

Capture2.PNG

Looks like maybe LWIP wasn't quite ready for prime time.

I saved a copy of the Vivado project, opened it in Vivado 2017.4.  I didn't recompile, but re-exported the hardware using the same bitstream (God knows the horrors of upgrading all of the IP cores).  Opened in SDK 2017.4, and all works perfectly

Rick

 

0 Kudos