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Participant jamsoft
Participant
1,638 Views
Registered: ‎11-22-2016

vdma + tpg calculations

Hello all,

 

please, help me to find the point(s) where I make mistake in my understanding and calculations...

 

I use TPG, VDMA and logiCVC in my design. Unfortunately, they have all different settings so I get a little confused..

 

The aim is to have 800x600 pixel picture on my screen (particularly in a window inside another window, see further)

 

The TPG is configured as follows:

 

Max number of columns: 800

Max number of lines: 600

Maximum data width: 8

Samples per clock: 1

 

From the TPG documentation  I have get that the value of data width 8 means 8 bits for one color component.

That gives me 24 bits for one pixel = 3 Bytes in RGB mode (i.e. RGB888)

 

Right?

 

The VDMA settings width and stride are in Byte units and the height setting is in No. of lines.

 

The read and write channels are enabled, 3 framebuffers mode, Stream Data width is set to 24 for both of channels.

 

The write channel is set as the Genlock Dynamic-Master with the s2mm tuser fsync mode.

 

The read channel is set as Dynamic-Slave with no fsync selected.

 

The Allow Unaligned Transfers option is not set for any channel.

 

 

The TPG video output is connected to the VDMA MM2S and input to the S2MM to create the closed chain even if it is set to ignore the input.

 

So from the above calculations I have set the VDMA in the following way:

 

MM2S side:

width: 800px * 3B/px = 2400 Bytes

height: 600 lines

stride: 800px * 3B/px = 2400 Bytes (I have tried also 0 value but result is the same...)

 

S2MM side:

width: 800px * 3B/px = 2400 Bytes

height: 600 lines

stride: 1024px * 3B/px = 3072 Bytes (for the 1024 value explanation see below, please)

 

framebuffers size: stride * height = 1843200 Bytes

 

There are 3 framebuffers and the VDMA is set to work in a circular mode.

 

The address of the last VDMA framebuffer is set  as the address of the logiCVC layer memory that shows the window on the background layer.

 

The logiCVC window layer is set as follows:

 

row stride: 1024 pixels   (note that all settings are in PIXELS not in BYTES as for the VDMA...)

This value is common for all layers

bit depth: 24 bpp

width: 800 px

height: 600 lines

mode: RGB

 

The background layer:

bit depth: 24 bpp

width: 1024 px

height: 768 px

mode: RGB

 

I have a nice background layer on the monitor screen with the 800x600px window shown. So the logiCVC mixer works great.

But the TPG patterns are not good inside the window. I see the patterns are changing if I change the TPG output pattern mode but the pattern picture inside the window is not proper.

 

If I write the bytes "manually" (with the memset or memcpy and also byte-by-byte in 2 for loops) into the window layer memory the picture is OK so the problem must lay somewhere in my calculations for the VDMA settings.

 

As the pattern in window changes when the TPG pattern is changed the shared memory settings are OK as well.

 

It also shows that the TPG and VDMA work "only" some settings are wrong...

 

Also, on the S2MM side I get the SOFLateErr  - Incoming frame size is greater than the programmed vsize value.

The number of lines is set accordingly in TPG and VDMA (600 lines). The error arises again after clearing it by writing 1 to the 11th bit of the S2MM status register as the VDMA manual recommends.

 

Can you help me to correct this issue, please?  

 

Thank you,

 

Jirka

 

 

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2 Replies
Participant jamsoft
Participant
1,616 Views
Registered: ‎11-22-2016

Re: vdma + tpg calculations

I have found one of my mistake...

 

The row stride for logiCVC is also in bytes...and the address of 1st pixel on each line is calculated as 4*row stride for the 24bpp.

 

Anyway it is not working even after adapting the VDMA for this...

 

Can someone advice how to set everything to make it working, please?

 

Or is there a way to convert the TPG RGB888 output to RGB332 (8bpp) or RGB565 (16px)? 

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Xilinx Employee
Xilinx Employee
1,512 Views
Registered: ‎08-02-2011

Re: vdma + tpg calculations

Do you still see the SOFLateErr in the VDMA?

Can you show a picture of what the behavior looks like? Or some ILA captures showing the incorrect behavior?
www.xilinx.com
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