UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor erigusaab
Visitor
5,803 Views
Registered: ‎12-22-2011

xemacpsif_dma: "strongly ordered" vs "uncached" memory?

This is a continuation of https://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/LWIP-echo-server-example-drops-delays-TX-packets-on-Zedboard/m-p/703732

 

Long story short: LWIP sample code from SDK 2016.1/2 doesn't work for me, eventually tracked down the cause to cache issues with EMAC DMA descriptors.

 

It would seem this commit is the cause of my problems:

 

https://github.com/Xilinx/embeddedsw/commit/80c849749a9009ca841d594a903a60fead4101aa

 

The commit message implies that "normal uncacheable" memory should be safe, but my testing indicates otherwise.

Tags (4)
0 Kudos