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Participant
Participant
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Registered: ‎10-27-2013

zynq interface to micrel ksz9021

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I am designing a custiom board with a xc7z020clg484-1 and micrel KSZ9021

 

on the ZYNQ : Banks 0,  500 and 501 are supplied with 3.3V

On the KSZ9021 is also supplied with 3.3V

 

When I configure this  in Vivado I get the following Waning:

 

[PS7 6] LVCMOS33 (3.3V) is not supported for RGMII interface in Ethernet0. Recomndation is to use 1.8/2.5V IO.

 

What does this mean?

Will the design still work, if I disisregard the warning  

Is the xc7z020clg484 going to be damaged?

 

 

 

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Anonymous
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Re: zynq interface to micrel ksz9021

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Yes, we managed to get the KSZ9021 working fine with 3.3V on bank 501. We did change a few settings in the setup for the RGMII settings, some just to avoid the warnings. We set RGMII pins to 2.5V in fast mode, it is actually still running@3.3V, but no warnings and is running with the correct drive strength.

 

Otherwise with the right uboot and address it worked fine at 3.3V@1Gb. It will still not be supported by Xilinx, but we haven't seen any issues. You do have to make sure your board is designed correctly with the right delays, otherwise you will have to play with the delay registers. Our board worked well with the delays we had and no design changes required.

 

You also have to make sure your Micrel chip gets reset properly after uboot to enable the RX/TX channels. The registers are identified in the respective documentation. It took us a few days to get it correct. We have two Linux builds that work, one with the specific KSZ9021 and one with the generic build using the standard protocol registers. 

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Community Manager
Community Manager
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Registered: ‎07-23-2012

Re: zynq interface to micrel ksz9021

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Hi,

 

"16.6.7 MIO Pin Considerations" section of Zynq TRM (UG585) states that LVCMOS33 is not supported with RGMII.

 

What is the value of VCCO_MIO? Having LVCMOS33 for RGMII interface doesn't damage the device if  "VCCO_MIO+0.55" is less than or equal to 3.3V. Otherwise, the FPGA can get damaged. (Refer to the attached screenshot).

 

Having said this, the correct functionality can't be assured since you are violating the recommendations.

 

Regards,

Krishna 

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Contributor
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Registered: ‎04-17-2014

Re: zynq interface to micrel ksz9021

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Hello,

 

I am in the same situation where I used 3.3V for bank 501, and are trying to use the RGMII interfaces.

 

Did you resolve your issue?  Did you need to change your board design?

 

 

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Anonymous
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10,630 Views

Re: zynq interface to micrel ksz9021

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Yes, we managed to get the KSZ9021 working fine with 3.3V on bank 501. We did change a few settings in the setup for the RGMII settings, some just to avoid the warnings. We set RGMII pins to 2.5V in fast mode, it is actually still running@3.3V, but no warnings and is running with the correct drive strength.

 

Otherwise with the right uboot and address it worked fine at 3.3V@1Gb. It will still not be supported by Xilinx, but we haven't seen any issues. You do have to make sure your board is designed correctly with the right delays, otherwise you will have to play with the delay registers. Our board worked well with the delays we had and no design changes required.

 

You also have to make sure your Micrel chip gets reset properly after uboot to enable the RX/TX channels. The registers are identified in the respective documentation. It took us a few days to get it correct. We have two Linux builds that work, one with the specific KSZ9021 and one with the generic build using the standard protocol registers. 

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Visitor
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Registered: ‎02-06-2015

Re: zynq interface to micrel ksz9021

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We also have 3.3V RGMII problem on my custom board (XC7Z030+KSZ9021RNI). The bank501 and KSZ9021 both powered with 3.3V.

 

The MDIO/MDC seems work OK, we can write to and readback from the Registers of the KSZ9021, and the auto-negotiation workable, but the RGMII not working.

 

Reset seems no problem, for we can get normal strapped-in hardware pin configurations from the KSZ9021 Registers (but we not route the RESET_N pin to bank501 as Zedboard/Marvell PHY do, just treat as KSZ9021 datasheet).

 

The TskewR delay is added as KSZ9021 datasheet requested.

 

We try LwIP code and Linux builds, both no data Tx/Rx..

 

If we have other omissions?

 

 

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Visitor
Visitor
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Registered: ‎11-04-2014

Re: zynq interface to micrel ksz9021

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Hi Lanceajones,

Is there anyway I can get a hold of you via email?
I am having the same problem and I'd love to know more about how you managed to get it working and how reliable it works.

I'm unsure if there are configuration parameters in uboot that sets the signal slew rate.

My email address is tni@iders.ca

Thanks,
Tian
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Visitor
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Registered: ‎08-26-2016

Re: zynq interface to micrel ksz9021

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We also did not notice the RGMII voltage recommendations and now have a custom board with 3.3V MIO bank and PHY chip. We will try the solutions listed here, but has anyone found out why 3.3V is not supported by Xilinx Zynq SoCs?  Is it a heat problem?  Speed problem?

 

Thanks,

J

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3,493 Views
Registered: ‎01-08-2012

Re: zynq interface to micrel ksz9021

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@johnzakelj wrote:

 

has anyone found out why 3.3V is not supported by Xilinx Zynq SoCs?  Is it a heat problem?  Speed problem?


 

The final version (v2.0) of the RGMII spec says "... RGMII ... will be based upon 1.5V HSTL interface voltages as defined by JEDEC EIA/JESD8-6 ... Class 1"

 

Xilinx 7 series SelectIO doesn't support HSTL 1 at 3.3V.

 

That said, earlier versions of the RGMII spec (e.g. v1.3) described 2.5V LVCMOS levels.

 

 

I suspect it can be made to work perfectly well at 3.3V (using LVCMOS33) and the limitation is due to overzealous software, not the Zynq silicon.

 

Regards,

Allan

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