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Participant
Participant
1,387 Views
Registered: ‎01-27-2019

[Common 17-161] Invalid option value '' specified for 'objects'. in 2018.3

I have one file which contains all the modules and logic in itself. I utilize SDx kernel Wizard to wrap this file as one RTL kernel. However, when I replace this file with the original files generated by Kernel Wizard itself and click generate RTL kernel, Vivado will always report

ERROR: [Common 17-161] Invalid option value '' specified for 'objects'.

I have checked several ARs which points out that the problem is becasue of there is a space in the project path or simulation file, but I don't have space. Besides, this file can be successfully synthesized and implemented.

Following is my log information:

# Start: RTL Kernel Packaging of Sources
#
source -notrace /home/jialezhang/Desktop/FPGA_TOP/FPGA_TOP/vivado_rtl_kernel/FPGA_TOP_ex/imports/package_kernel.tcl
# Packaging project
package_project /home/jialezhang/Desktop/FPGA_TOP/FPGA_TOP/vivado_rtl_kernel/FPGA_TOP_ex/FPGA_TOP mycompany.com kernel FPGA_TOP
INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'clock' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'clock': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'.
WARNING: [IP_Flow 19-3153] Bus Interface 'clock': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
ERROR: [Common 17-161] Invalid option value '' specified for 'objects'.

 

My SDx version is 2018.3, who can help me? Thx!

 

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Teacher
Teacher
1,358 Views
Registered: ‎10-23-2018

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Xilinx Employee
Xilinx Employee
1,349 Views
Registered: ‎10-19-2015

Hi @rookicoe 

I think @xilinxacct is correct, I also agree with the null pointer assertion 

I solved a similar error in a different thread by fixing a null pointer or poorly formed command. 

https://forums.xilinx.com/t5/SDAccel/Specifying-frequency-of-ap-clk-and-ap-clk-2-in-SDx/m-p/930240#M3133 

ERROR: [Vivado 12-385] Illegal file or directory name '' 

What i like to do when debugging a script is run each line of the script one at a time until you find the failure, size of the script permitting. 

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Participant
Participant
1,330 Views
Registered: ‎01-27-2019

Well! Thank you so much! You provide me with a very good way to debug. I will try it, if I have later problem I will poster it!

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Participant
Participant
1,320 Views
Registered: ‎01-27-2019

Hi @mcertosi ! I have met a strange problem. I firstly disable all the line in the package_kernel.tcl file and click Generate RTL Kernel in GUI interface. It still shows me the same error information below.

# Start: RTL Kernel Packaging of Sources
#source -notrace /home/jialezhang/Desktop/FPGATOP2/FPGATOP2/vivado_rtl_kernel/FPGATOP_ex/imports/package_kernel.tcl
# Removing Directory: '/home/jialezhang/Desktop/FPGATOP2/FPGATOP2/vivado_rtl_kernel/FPGATOP_ex/FPGATOP'
# Packaging project
package_project /home/jialezhang/Desktop/FPGATOP2/FPGATOP2/vivado_rtl_kernel/FPGATOP_ex/FPGATOP test kernel FPGATOP
INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'clock' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'clock': Added interface parameter 'ASSOCIATED_RESET' with value 'reset'.
WARNING: [IP_Flow 19-3153] Bus Interface 'clock': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
ERROR: [Common 17-161] Invalid option value '' specified for 'objects'.

 

There is nothing in the package_kernel.tcl file, but why it will still shows these information. And besides package_kernel.tcl file, is there any other file I should read and modify?

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Xilinx Employee
Xilinx Employee
1,313 Views
Registered: ‎10-19-2015

Hi @rookicoe 

What are you trying to build? Where did all the scripts come from?

The tools are running other commands so there must be something going on in your script. 

I'll need you to post the full script and the output as well as the entire project context (tool version, acceleration card, DSA version, XRT version, scripts, make file) 

Usually this "invalid option" problem comes from a "get_property" or "get_<objects>" command that doesn't return anything. 

Regards,

M

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Participant
Participant
1,297 Views
Registered: ‎01-27-2019

I want to build an application(I m sorry that I cannot tell the detail about it), and this application is a Kernel which can be synthesized and implemented successfully. And what I use is SDx 2018.3 with ALVEOu280-es board, SDx will automatically choose SDAccel for me to run this project. The following is what I do:

1. Open SDx 2018.3, choose the correct board and open an empty application

2. Open RTL Kernel Wizard and SDAccel will call Vivado 2018.3 for me.

3. Set the port information such as how many scalar and how many master ports. For this project, I have zero scalar port and four memory mapping ports and one dma ports, so I choose five master ports.

4. Kernel Wizard will generate some example design sources and simulation sources for me. I remove all these files from the original project.

5. I add my application project in the design source. This one file include all the necessary modules and logic, which can be synthesized and implemented successfully.

6. Finally, I click the Generate RTL Kernel, which gives me the error message I have postered before.

I have attached the package_kernel.tcl file, this file is automatically generated by Vivado. What I do is click the button in the GUI. And the following is the top module port information, you might check it, because I don't know whether my setting is right or not.(You can consider master as slave, and slave as master, the view might be different, so the port will be completely inverse.)

input clock,
input reset,
output io_master_aw_ready,
input io_master_aw_valid,
input [24:0] io_master_aw_bits_addr,
input [7:0] io_master_aw_bits_len,
input [2:0] io_master_aw_bits_size,
input [1:0] io_master_aw_bits_burst,
input io_master_aw_bits_lock,
input [3:0] io_master_aw_bits_cache,
input [2:0] io_master_aw_bits_prot,
input [3:0] io_master_aw_bits_qos,
input [3:0] io_master_aw_bits_region,
input [11:0] io_master_aw_bits_id,
input io_master_aw_bits_user,
output io_master_w_ready,
input io_master_w_valid,
input [31:0] io_master_w_bits_data,
input io_master_w_bits_last,
input [11:0] io_master_w_bits_id,
input [3:0] io_master_w_bits_strb,
input io_master_w_bits_user,
input io_master_b_ready,
output io_master_b_valid,
output [1:0] io_master_b_bits_resp,
output [11:0] io_master_b_bits_id,
output io_master_b_bits_user,
output io_master_ar_ready,
input io_master_ar_valid,
input [24:0] io_master_ar_bits_addr,
input [7:0] io_master_ar_bits_len,
input [2:0] io_master_ar_bits_size,
input [1:0] io_master_ar_bits_burst,
input io_master_ar_bits_lock,
input [3:0] io_master_ar_bits_cache,
input [2:0] io_master_ar_bits_prot,
input [3:0] io_master_ar_bits_qos,
input [3:0] io_master_ar_bits_region,
input [11:0] io_master_ar_bits_id,
input io_master_ar_bits_user,
input io_master_r_ready,
output io_master_r_valid,
output [1:0] io_master_r_bits_resp,
output [31:0] io_master_r_bits_data,
output io_master_r_bits_last,
output [11:0] io_master_r_bits_id,
output io_master_r_bits_user,
output io_dma_aw_ready,
input io_dma_aw_valid,
input [63:0] io_dma_aw_bits_addr,
input [7:0] io_dma_aw_bits_len,
input [2:0] io_dma_aw_bits_size,
input [1:0] io_dma_aw_bits_burst,
input io_dma_aw_bits_lock,
input [3:0] io_dma_aw_bits_cache,
input [2:0] io_dma_aw_bits_prot,
input [3:0] io_dma_aw_bits_qos,
input [3:0] io_dma_aw_bits_region,
input [5:0] io_dma_aw_bits_id,
input io_dma_aw_bits_user,
output io_dma_w_ready,
input io_dma_w_valid,
input [511:0] io_dma_w_bits_data,
input io_dma_w_bits_last,
input [5:0] io_dma_w_bits_id,
input [63:0] io_dma_w_bits_strb,
input io_dma_w_bits_user,
input io_dma_b_ready,
output io_dma_b_valid,
output [1:0] io_dma_b_bits_resp,
output [5:0] io_dma_b_bits_id,
output io_dma_b_bits_user,
output io_dma_ar_ready,
input io_dma_ar_valid,
input [63:0] io_dma_ar_bits_addr,
input [7:0] io_dma_ar_bits_len,
input [2:0] io_dma_ar_bits_size,
input [1:0] io_dma_ar_bits_burst,
input io_dma_ar_bits_lock,
input [3:0] io_dma_ar_bits_cache,
input [2:0] io_dma_ar_bits_prot,
input [3:0] io_dma_ar_bits_qos,
input [3:0] io_dma_ar_bits_region,
input [5:0] io_dma_ar_bits_id,
input io_dma_ar_bits_user,
input io_dma_r_ready,
output io_dma_r_valid,
output [1:0] io_dma_r_bits_resp,
output [511:0] io_dma_r_bits_data,
output io_dma_r_bits_last,
output [5:0] io_dma_r_bits_id,
output io_dma_r_bits_user,
input io_slave_0_aw_ready,
output io_slave_0_aw_valid,
output [33:0] io_slave_0_aw_bits_addr,
output [7:0] io_slave_0_aw_bits_len,
output [2:0] io_slave_0_aw_bits_size,
output [1:0] io_slave_0_aw_bits_burst,
output io_slave_0_aw_bits_lock,
output [3:0] io_slave_0_aw_bits_cache,
output [2:0] io_slave_0_aw_bits_prot,
output [3:0] io_slave_0_aw_bits_qos,
output [3:0] io_slave_0_aw_bits_region,
output [15:0] io_slave_0_aw_bits_id,
output io_slave_0_aw_bits_user,
input io_slave_0_w_ready,
output io_slave_0_w_valid,
output [63:0] io_slave_0_w_bits_data,
output io_slave_0_w_bits_last,
output [15:0] io_slave_0_w_bits_id,
output [7:0] io_slave_0_w_bits_strb,
output io_slave_0_w_bits_user,
output io_slave_0_b_ready,
input io_slave_0_b_valid,
input [1:0] io_slave_0_b_bits_resp,
input [15:0] io_slave_0_b_bits_id,
input io_slave_0_b_bits_user,
input io_slave_0_ar_ready,
output io_slave_0_ar_valid,
output [33:0] io_slave_0_ar_bits_addr,
output [7:0] io_slave_0_ar_bits_len,
output [2:0] io_slave_0_ar_bits_size,
output [1:0] io_slave_0_ar_bits_burst,
output io_slave_0_ar_bits_lock,
output [3:0] io_slave_0_ar_bits_cache,
output [2:0] io_slave_0_ar_bits_prot,
output [3:0] io_slave_0_ar_bits_qos,
output [3:0] io_slave_0_ar_bits_region,
output [15:0] io_slave_0_ar_bits_id,
output io_slave_0_ar_bits_user,
output io_slave_0_r_ready,
input io_slave_0_r_valid,
input [1:0] io_slave_0_r_bits_resp,
input [63:0] io_slave_0_r_bits_data,
input io_slave_0_r_bits_last,
input [15:0] io_slave_0_r_bits_id,
input io_slave_0_r_bits_user,
input io_slave_1_aw_ready,
output io_slave_1_aw_valid,
output [33:0] io_slave_1_aw_bits_addr,
output [7:0] io_slave_1_aw_bits_len,
output [2:0] io_slave_1_aw_bits_size,
output [1:0] io_slave_1_aw_bits_burst,
output io_slave_1_aw_bits_lock,
output [3:0] io_slave_1_aw_bits_cache,
output [2:0] io_slave_1_aw_bits_prot,
output [3:0] io_slave_1_aw_bits_qos,
output [3:0] io_slave_1_aw_bits_region,
output [15:0] io_slave_1_aw_bits_id,
output io_slave_1_aw_bits_user,
input io_slave_1_w_ready,
output io_slave_1_w_valid,
output [63:0] io_slave_1_w_bits_data,
output io_slave_1_w_bits_last,
output [15:0] io_slave_1_w_bits_id,
output [7:0] io_slave_1_w_bits_strb,
output io_slave_1_w_bits_user,
output io_slave_1_b_ready,
input io_slave_1_b_valid,
input [1:0] io_slave_1_b_bits_resp,
input [15:0] io_slave_1_b_bits_id,
input io_slave_1_b_bits_user,
input io_slave_1_ar_ready,
output io_slave_1_ar_valid,
output [33:0] io_slave_1_ar_bits_addr,
output [7:0] io_slave_1_ar_bits_len,
output [2:0] io_slave_1_ar_bits_size,
output [1:0] io_slave_1_ar_bits_burst,
output io_slave_1_ar_bits_lock,
output [3:0] io_slave_1_ar_bits_cache,
output [2:0] io_slave_1_ar_bits_prot,
output [3:0] io_slave_1_ar_bits_qos,
output [3:0] io_slave_1_ar_bits_region,
output [15:0] io_slave_1_ar_bits_id,
output io_slave_1_ar_bits_user,
output io_slave_1_r_ready,
input io_slave_1_r_valid,
input [1:0] io_slave_1_r_bits_resp,
input [63:0] io_slave_1_r_bits_data,
input io_slave_1_r_bits_last,
input [15:0] io_slave_1_r_bits_id,
input io_slave_1_r_bits_user,
input io_slave_2_aw_ready,
output io_slave_2_aw_valid,
output [33:0] io_slave_2_aw_bits_addr,
output [7:0] io_slave_2_aw_bits_len,
output [2:0] io_slave_2_aw_bits_size,
output [1:0] io_slave_2_aw_bits_burst,
output io_slave_2_aw_bits_lock,
output [3:0] io_slave_2_aw_bits_cache,
output [2:0] io_slave_2_aw_bits_prot,
output [3:0] io_slave_2_aw_bits_qos,
output [3:0] io_slave_2_aw_bits_region,
output [15:0] io_slave_2_aw_bits_id,
output io_slave_2_aw_bits_user,
input io_slave_2_w_ready,
output io_slave_2_w_valid,
output [63:0] io_slave_2_w_bits_data,
output io_slave_2_w_bits_last,
output [15:0] io_slave_2_w_bits_id,
output [7:0] io_slave_2_w_bits_strb,
output io_slave_2_w_bits_user,
output io_slave_2_b_ready,
input io_slave_2_b_valid,
input [1:0] io_slave_2_b_bits_resp,
input [15:0] io_slave_2_b_bits_id,
input io_slave_2_b_bits_user,
input io_slave_2_ar_ready,
output io_slave_2_ar_valid,
output [33:0] io_slave_2_ar_bits_addr,
output [7:0] io_slave_2_ar_bits_len,
output [2:0] io_slave_2_ar_bits_size,
output [1:0] io_slave_2_ar_bits_burst,
output io_slave_2_ar_bits_lock,
output [3:0] io_slave_2_ar_bits_cache,
output [2:0] io_slave_2_ar_bits_prot,
output [3:0] io_slave_2_ar_bits_qos,
output [3:0] io_slave_2_ar_bits_region,
output [15:0] io_slave_2_ar_bits_id,
output io_slave_2_ar_bits_user,
output io_slave_2_r_ready,
input io_slave_2_r_valid,
input [1:0] io_slave_2_r_bits_resp,
input [63:0] io_slave_2_r_bits_data,
input io_slave_2_r_bits_last,
input [15:0] io_slave_2_r_bits_id,
input io_slave_2_r_bits_user,
input io_slave_3_aw_ready,
output io_slave_3_aw_valid,
output [33:0] io_slave_3_aw_bits_addr,
output [7:0] io_slave_3_aw_bits_len,
output [2:0] io_slave_3_aw_bits_size,
output [1:0] io_slave_3_aw_bits_burst,
output io_slave_3_aw_bits_lock,
output [3:0] io_slave_3_aw_bits_cache,
output [2:0] io_slave_3_aw_bits_prot,
output [3:0] io_slave_3_aw_bits_qos,
output [3:0] io_slave_3_aw_bits_region,
output [15:0] io_slave_3_aw_bits_id,
output io_slave_3_aw_bits_user,
input io_slave_3_w_ready,
output io_slave_3_w_valid,
output [63:0] io_slave_3_w_bits_data,
output io_slave_3_w_bits_last,
output [15:0] io_slave_3_w_bits_id,
output [7:0] io_slave_3_w_bits_strb,
output io_slave_3_w_bits_user,
output io_slave_3_b_ready,
input io_slave_3_b_valid,
input [1:0] io_slave_3_b_bits_resp,
input [15:0] io_slave_3_b_bits_id,
input io_slave_3_b_bits_user,
input io_slave_3_ar_ready,
output io_slave_3_ar_valid,
output [33:0] io_slave_3_ar_bits_addr,
output [7:0] io_slave_3_ar_bits_len,
output [2:0] io_slave_3_ar_bits_size,
output [1:0] io_slave_3_ar_bits_burst,
output io_slave_3_ar_bits_lock,
output [3:0] io_slave_3_ar_bits_cache,
output [2:0] io_slave_3_ar_bits_prot,
output [3:0] io_slave_3_ar_bits_qos,
output [3:0] io_slave_3_ar_bits_region,
output [15:0] io_slave_3_ar_bits_id,
output io_slave_3_ar_bits_user,
output io_slave_3_r_ready,
input io_slave_3_r_valid,
input [1:0] io_slave_3_r_bits_resp,
input [63:0] io_slave_3_r_bits_data,
input io_slave_3_r_bits_last,
input [15:0] io_slave_3_r_bits_id,
input io_slave_3_r_bits_user

Besides, I think that XRT and DSA has not been used here actually.

 

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Participant
Participant
1,257 Views
Registered: ‎01-27-2019

Hi @mcertosi , I have located the problem after I carefully run each line of package_kernel.tcl file, the error will be presented when I run:

set_property value 64 $bifparam

set_property value_source constant $bifparam

I believe that all set_property commands in edit_core function will return the error [Common 17-161]: Invalid option value '' specified for 'objects'. in 2018.3.

Do you know how can I fix this problem? I have attached the port information and tcl file in the last reply. Thx

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