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Explorer
Explorer
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Registered: ‎06-14-2018

Data transfer, strange behavior when starting

Hi,

I'm testing data transfer, HW simulation, on a 512*512*8bpp image. Here's the code:

#include <ap_int.h>
#include "host.h"

#define DATAWIDTH   512
typedef ap_uint<DATAWIDTH> uint512_dt;

extern "C" {
	void sobel( uint512_dt *inimg, uint512_dt *outimg ) {
		#pragma HLS INTERFACE m_axi port=inimg offset=slave bundle=gmem max_read_burst_length=64 max_write_burst_length=64
		#pragma HLS INTERFACE m_axi port=outimg offset=slave bundle=gmem max_read_burst_length=64 max_write_burst_length=64
		#pragma HLS INTERFACE s_axilite port=inimg  bundle=control
		#pragma HLS INTERFACE s_axilite port=outimg bundle=control
		#pragma HLS INTERFACE s_axilite port=return bundle=control

		uint512_dt local_buffer;

		loop_read: for(int line = 0; line < 64*64;  line++) {
			#pragma HLS PIPELINE
			local_buffer = inimg[line];
			outimg[line] = local_buffer;
		}
	}
}

I can reach 100% efficiency, 18927.400 MB/s.

My question is about the Application Timeline screenshot. Why aren't the very first transfers grouped by 5, like they are all over the kernel execution ?

Here, we have 3, then 5, 5, 5 etc. transfers.

Also there's only two writes at the beginning where we should expect 3 according to the 3 reads.

 

Screenshot from 2019-04-16 12-38-38.png
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1 Reply
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Moderator
Moderator
323 Views
Registered: ‎11-04-2010

For such issue, you have to check the result of hw_emu at the same time and research the control signal of the AXI port.

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