11-19-2018 01:26 AM - edited 11-22-2018 06:04 AM
I have a file with 4-bit binary data, and I want to read it using the following code:
typedef ap_uint<4> weight_t;
weight_t *w[NUMBER_WEIGHTS_ONLY];
for(int i=0;i<NUMBER_WEIGHTS_ONLY;i++){
w[i] = (weight_t *) sds_alloc(sizeof(weight_t)*16);
}
std::ifstream in3("Filename.dat",std::ios_base::binary); for (int i=0;i<NUMBER_WEIGHTS_ONLY;i++) { in3.read((char *)w[i],sizeof(weight_t)*weights_weights[i]); }
I get the following error on building the project:
Interface parameter bitwidth 'weight.V' (/home/akshay/PhD/workspace_SDx/Lenet_cifar_Kmean_indexed/src/conv_hw.cpp:17:1) must be a multiple of 8 for AXI4 master port. ERROR: [HLS 200-70] Failed building synthesis data model.
Please help me with a solution for this.
If I use "typedef ap_uint<8> weight_t;" then everything is synthesized, but my output is incorrect as now 8-bits are read instead of 4.
Please help!!
--Akshay
12-11-2018 06:13 PM
You need to change your host code to correctly parse your output data.
12-11-2018 10:29 PM
Hi @brucey,
Thank you for your reply.
Does it mean I can not directly use the data with size less than 8-bits for AXI interfacing?
I have to maybe concatenate the data on host and then store as a single word of 8 bits in DDR?
And, then again on the FPGA I have to read the 8 bit data from DDR and then separate into two 4-bit values?
Thanks,
Akshay
12-19-2018 08:26 PM
Hi, @akshayjrkp ,
Does it mean I can not directly use the data with size less than 8-bits for AXI interfacing?
Yes, you cannot directly use the data with size less than 8-bits for AXI interface because of protocol requirement.
I have to maybe concatenate the data on host and then store as a single word of 8 bits in DDR?
Yes.
And, then again on the FPGA I have to read the 8 bit data from DDR and then separate into two 4-bit values?
Yes