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sfhoover
Newbie
Newbie
1,743 Views
Registered: ‎03-22-2019

RTL Kernel Waveform

I am creating an RTL Kernel using SDAccel/Vivado, starting from the RTL Kernel Wizard. I can run the Kernel in Vivado using a testbench modified from the one provided by the Wizard and see all internal signals. This simulation looks fine.

I am now trying to debug a hang when running Hardware Emulation. I have selected Host Debug and Kernel Debug in Project Settings, and I have selected "Use waveform for kernel debugging" and "Launch live waveform" in the Run Configuration. The live waveform shows waveforms from OpenCL, but does not appear to include internal signals in the RTL kernel. This seems consistent with the documentation.

Is there a way to generate a waveform of internal signals of the RTL kernel in Hardware Emulation mode? It seems there should be. The kernel is running in simulation. I'm a bit confused as to why this does not seem to be standard practice and why I cannot find a clear answer online.

Thanks in advance.

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kmorris
Xilinx Employee
Xilinx Employee
1,640 Views
Registered: ‎01-11-2011

Hi @sfhoover, during the live waveform are you not able to see your RTL kernel signals in the objects window of the simulation? These signals should show up during a HW Emulation simulation, unless there are aspects of the design that are encrypted, such as IP.

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peffers
Visitor
Visitor
1,493 Views
Registered: ‎02-11-2019

I have found that you can have hw emulation generate a waveform in non-interactive simulations and then view them with vivado. This may be more convenient depending on your workflow.

 

Create an sdaccel.ini file in the directory you are running from:

[Emulation]
launch_waveform=batch
[Debug]
profile=true
timeline_trace=true
device_profile=true

 

Create open_waves.tcl:

current_fileset
open_wave_database <path to .wdb file>

 

View the waveform:

vivado -source open_waves.tcl

 

 

 

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sfhoover
Newbie
Newbie
1,483 Views
Registered: ‎03-22-2019

Thanks, Kevin(?) And Simon(?). (Small community, I guess.) I'm currently focused on enabling open source development flows for F1. (See github/fpga-webserver.), but next time I am running Xilinx flows for debug, I'll try this again with your suggestions.

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