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w.hzhang86
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Registered: ‎12-14-2018

RTL code working the Vivado 2017.1 not synthesizable with Vivado 2018.2 on aws-f1

I'm trying the latest aws-fpga. The F1 instance has the latest AMI 1.50 and Vivado 2018.2 installed.
For some reason, I have to base my design on the cl_dram_dma example from a previous aws-fpga commit (https://github.com/aws/aws-fpga/tree/934000f9a57c0cde8786441864d5c6e0cf42fef9/hdk/cl/examples/cl_dram_dma). So first, I copied cl_dram_dma from the old aws-fpga branch and tried it within the new aws-fpga framework and the new Vivdado 2018.2. It works. Then, I ran my own design as before, but synthesizing stopped after a few minutes. Here's the error message I found in *.vivado.log file:
 
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (28#1) [/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v:474]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_15_axi_register_slice' (29#1) [/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v:2300]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice' (30#1) [/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice/synth/axi_register_slice.v:58]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/centos/src/project_data/aws-fpga/hdk/cl/examples/Hui_HelloSpatial_hw/build/src_post_encryption/cl_dram_dma.sv:1004]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/centos/src/project_data/aws-fpga/hdk/cl/examples/Hui_HelloSpatial_hw/build/src_post_encryption/cl_dma_pcis_slv.sv:16]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/centos/src/project_data/aws-fpga/hdk/cl/examples/Hui_HelloSpatial_hw/build/src_post_encryption/cl_dram_dma.sv:18]
 
I backtracked the log file and found the most recent WARNING to the error, not sure if it helps:
 
Running synth_design for cl_dram_dma /home/centos/src/project_data/aws-fpga/hdk/cl/examples/Hui_HelloSpatial_hw/build/scripts [Wed Feb 06 18:42:43 2019]
Command: synth_design -top cl_dram_dma -verilog_define XSDB_SLV_DIS -part xcvu9p-flgb2104-2-i -mode out_of_context -keep_equivalent_registers -flatten_hierarchy rebuilt -max_uram_cascade_height 1 -directive default
Starting synth_design
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Implementation target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice_light/axi_register_slice_light.xci
/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice/axi_register_slice.xci
/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/dest_register_slice/dest_register_slice.xci
/home/centos/src/project_data/aws-fpga/hdk/common/shell_v04261818/design/ip/src_register_slice/src_register_slice.xci
 
Do you have any clues of what the problem could be? Thanks
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hongh
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Moderator
576 Views
Registered: ‎11-04-2010

Hi, @w.hzhang86 ,

The issue is related to AWS platform, so it is better to be supported in AWS F1 forum:

https://forums.aws.amazon.com/forum.jspa?forumID=243&start=0

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