11-21-2018 10:03 AM - edited 11-21-2018 10:05 AM
I am using SDAccel v2018.2. When having read_pipe /write_pipe, in order to build FPGA binaries I need:
A) --xp param:compiler.version=31
B) a dummy pointer arg in kernels that do not need a pointer global memory, as explained in: https://forums.xilinx.com/t5/SDAccel/ERROR-KernelCheck-83-114-in-sdx-2017-4/td-p/818135
I noticed that when using instead the blocking counterparts (read_pipe_block & write_pipe_block) I do NOT need A) nor B)
However, I need the non-blocking versions in my design, is there any workaround to avoid those dummy pointers?
Also I couldn't find any examples in the Github repor with NON-blocking pipe functions.
Any help would be greatly appreciated!
11-22-2018 11:17 PM
Hi， @leonardo.solis ,
Pipes can only be accessed using standard OpenCL read_pipe() and write_pipe() built-in functions in non-blocking mode, or using Xilinx® extended read_pipe_block() and write_pipe_block() functions in blocking mode.
Currently we don't have the existing example for non-blocking mode read_pipe()/write_pipe() in standard OpenCL.
Could you show us why you cannot use the blocking mode pipe operation?
12-14-2018 02:09 AM
I am attaching a small example code that uses pipes in non-blocking mode: a chain of three kernels connected with two pipes. It is based on Xilinx SDx 2018.2 example:
As a result: when using non-blocking pipe READS, the design hangs indefinitely on AWS EC2 F1 (only software emulation runs and finishes as expected). On the contrary, enabling ONLY non-blocking WRITE functions, made it worked in all cases.
In the README.md file you can find the info on how to build and run.
Looking forward to hearing from you,
12-20-2018 01:28 PM
Hi, @leonardo.solis ,
I just confirmed with the factory: currently the Non-blocking pipe is not supported in SDAccel. The feature is still on the roadmap.
Sorry for the inconvenience.