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Visitor troore
Visitor
108 Views
Registered: ‎08-02-2017

[AWS F1, SDAccel, PCIe] Multiple FPGAs peer to peer data transfer

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Hi,

We know CUDA supports peer to peer data transfer between multiple GPUs that are connected by a PCIe switch tree. Like,

pcie.PNG

 

via API cudaMemcpyPeerAsync like,

 

for( int i=0; i<num_gpus-1; i++ ) 
    cudaMemcpyPeerAsync( d_a[i+1], device[i+1], d_a[i], device[i], num_bytes, stream[i] );

Then the GPUs could communication in the following way:

right.PNG

So I wonder if SDAccel supports such mechanism between FPGAs in a single node connected by PCIe switch tree, like the scenario of AWS F1. I found an example:

https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/host/multiple_devices_ocl

But I don't know if it is the right way to implement the peer to peer communication.

 

Thanks,

-troore

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1 Solution

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Xilinx Employee
Xilinx Employee
88 Views
Registered: ‎03-24-2010

Re: [AWS F1, SDAccel, PCIe] Multiple FPGAs peer to peer data transfer

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For general peer-to-peer support on U200,U250 is scheduled in 2019.1.

For non-Xilinx platform support on peer to peer, please check it with vendors.

Regards,
brucey
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3 Replies
Xilinx Employee
Xilinx Employee
89 Views
Registered: ‎03-24-2010

Re: [AWS F1, SDAccel, PCIe] Multiple FPGAs peer to peer data transfer

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For general peer-to-peer support on U200,U250 is scheduled in 2019.1.

For non-Xilinx platform support on peer to peer, please check it with vendors.

Regards,
brucey
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Give Kudos to a post which you think is helpful and reply oriented.
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Visitor troore
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75 Views
Registered: ‎08-02-2017

Re: [AWS F1, SDAccel, PCIe] Multiple FPGAs peer to peer data transfer

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Hi brucey,

I see. Thanks for your reply.

 

Thanks,

-troore

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Visitor troore
Visitor
68 Views
Registered: ‎08-02-2017

Re: [AWS F1, SDAccel, PCIe] Multiple FPGAs peer to peer data transfer

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Hi @brucey,

Will only U200, U250 boards be considered? What about other boards?

Thanks,

-troore

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