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Registered: ‎03-04-2019

[CF2XD 83-1302] error during hardware synthesis

I am using OpenCL pipes to transfer data from 1 kernel to another kernel. 

I have 2 pipes initialized to 32kb size and 2 kernels which are called recursively. The kernels are called concurrently and each one has a different command queue. 

.

.

kernel 1 {read pipe0 writes pipe 1}

clFinish(kernel2_command)

kernel 2 {read pipe1 writes pipe 0}

clFinish(kernel1_command)

kernel 1 {read pipe0 writes pipe 1}

clFinish(kernel2_command)

kernel 2 {read pipe1 writes pipe 0}

clFinish(kernel1_command)

.

.

However this code passed the sw_emu but generates the below error while doing hardware synthesis. What might be the reason for this error. 

setting depth of 32768 for xcl_pipe_pipepath0
setting depth of 32768 for xcl_pipe_pipepath1
ERROR: [CF2XD 83-1302] Port xcl_pipe_pipepath0.M_AXIS already assigned (xcl_pipe_pipepath0.M_AXIS --> depthwise_1.pipepath0_pipe)
/opt/Xilinx/SDx/2018.3.op2405991/bin/cf2xd: line 18: 5990 Segmentation fault ${BIN_DIR}/unwrapped/lnx64.o/`basename ${LOADER}` ${ARGS}
Error generating intermediate design file dr.xml
Error creating IPI .bd design file, exiting
ERROR: [XOCC 60-398] sdx_link failed
ERROR: [XOCC 60-626] Kernel link failed to complete
ERROR: [XOCC 60-703] Failed to finish linking

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Moderator
Moderator
246 Views
Registered: ‎11-04-2010

Re: [CF2XD 83-1302] error during hardware synthesis

I suggest you develop C++ kernel instead of OpenCL kernel, because you can get more optiomization methods for C++ kernel.

Example for Kernel to Kernel communication, you can refer to the below example:

https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/host/streaming_k2k_mm/src

 

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