07-13-2017 03:07 PM
What is the current status of accelerating an infrastructure like Caffe (or Tensorflow) on Xilinx FPGAs? What is the best available porting of Caffe to Xilinx FPGAs so far?
I can find papers
07-17-2017 10:37 AM
At the time of this writing, there is a Mipsology Caffe implementation for many networks on AWS - Zebra Deep Learning Accelerator.
In the near future, there will be Caffe, MXNet, and TensorFlow int8 optimized IPs available from Xilinx.
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07-18-2017 05:15 AM
The development that you'll want to follow is the reVISION stack:
which is rolling out as we speak. Initial support will be for Caffe and you can access some of the demo designs today.
You should talk to your local FAE about getting access.
07-20-2017 02:24 PM
I haven't really documented much for that repository so far, but if you have any questions you can shoot me an e-mail (e-mail is in the paper). Note that the current spin supports only 3x3, 1x1, and 5x5 convolutions with unit stride. Some updates will probably be released in the next couple of months to add more features (e.g. ReLU, pooling, etc.).