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Caffe on FPGA

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Adventurer
Adventurer
Posts: 54
Registered: ‎03-22-2017

Caffe on FPGA

What is the current status of accelerating an infrastructure like Caffe (or Tensorflow) on Xilinx FPGAs? What is the best available porting of Caffe to Xilinx FPGAs so far?

 

I can find papers

https://arxiv.org/pdf/1609.09671.pdf

 

repositories

https://github.com/dicecco1/fpga_caffe

https://github.com/BenBBear/VCNN

 

and tutorials

https://www.embedded-vision.com/news/caffe-zynq-state-art-machine-learning-inference-performance-less-5-watts-free-webinar-xilinx

 

Thank you

Xilinx Employee
Posts: 66
Registered: ‎06-07-2016

Re: Caffe on FPGA

Hi @gdg

 

At the time of this writing, there is a Mipsology Caffe implementation for many networks on AWS - Zebra Deep Learning Accelerator.

 

There is also a Xilinx AlexNet on Caffe platform on Nimbix you can try out. This was implemented in SDAccel with this IP.

  

In the near future, there will be Caffe, MXNet, and TensorFlow int8 optimized IPs available from Xilinx.

 

Sign-up for release notifications here:

https://www.xilinx.com/applications/megatrends/machine-learning.html

  

Best,

-Dutch

Xilinx Employee
Posts: 3,588
Registered: ‎08-02-2011

Re: Caffe on FPGA

Hello,

 

The development that you'll want to follow is the reVISION stack:

https://www.xilinx.com/products/design-tools/embedded-vision-zone.html

 

which is rolling out as we speak. Initial support will be for Caffe and you can access some of the demo designs today.

 

You should talk to your local FAE about getting access.

www.xilinx.com
Visitor
Posts: 5
Registered: ‎06-24-2016

Re: Caffe on FPGA

I haven't really documented much for that repository so far, but if you have any questions you can shoot me an e-mail (e-mail is in the paper). Note that the current spin supports only 3x3, 1x1, and 5x5 convolutions with unit stride. Some updates will probably be released in the next couple of months to add more features (e.g. ReLU, pooling, etc.).