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Visitor nahmad16
Visitor
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Registered: ‎10-18-2018

Hardware Simulation generating approximate timing

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Hello,

I am trying to run hardware simulation of an OpenCL/C++ kernel using SDAccel. I am using the following command line:

make check TARGETS=hw_emu DEVICES=$AWS_PLATFORM all

I get the following info in the output:

INFO: [SDX-EM 01] Hardware emulation runs simulation underneath. Using a large data set will result in long simulation times. It is recommended that a small dataset is used for faster execution. This flow does not use cycle accurate models and hence the performanc edata generated is approximate.

In the SDAccel Environment guide, they get the following message instead when they do hardware simulation:

INFO: [SDx-EM 01] Hardware emulation runs detailed simulation underneath.
It may take long time for large data set. Please use a small dataset for
faster execution. You can still get performance trend for your kernel
with smaller dataset.
 
Why am I not getting detailed simulation underneath? Thanks for your help!!
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Moderator
Moderator
497 Views
Registered: ‎11-04-2010

Re: Hardware Simulation generating approximate timing

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Hi, @nahmad16,

In my opinion:

The Performance estimation obtained from hw_emu are quite close to the real result, but it cannot be used as a sign-off result. It will be a good guidence for user to understand the whole system performance.

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Moderator
Moderator
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Registered: ‎11-04-2010

Re: Hardware Simulation generating approximate timing

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Hi, @nahmad16 ,

 

It's just the change of the printed message with version updating, actually the backend simulation do the same work.  

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Visitor nahmad16
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Registered: ‎10-18-2018

Re: Hardware Simulation generating approximate timing

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Hi Hongh,

Thanks for your reply.

Does it mean hardware emulation is not cycle accurate and I cannot use it to get performance estimates? Due to prohibitive compilation times for hardware, I would like to use hardware emulation instead to get performance estimates. How should I go about it?

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Moderator
Moderator
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Registered: ‎11-04-2010

Re: Hardware Simulation generating approximate timing

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Hi, @nahmad16 ,

Hope the below content in UG1023 can help you:

Hardware emulation provides performance and resource estimation, allowing the programmer to get an insight into the design.

The DDR memory model and the Memory Interface Generator (MIG) model used in Hardware Emulation are high-level simulation models. These models are good for simulation performance, however they approximate latency values and are not cycle-accurate like the kernels.
Consequently, any performance numbers shown in the profile summary report are approximate, and must be used only as a general guidance and for comparing relative performance between different kernel implementations.

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Visitor nahmad16
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Registered: ‎10-18-2018

Re: Hardware Simulation generating approximate timing

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Hi Hongh. Thanks for your reply.

In UG1277 (v2018.2) June 6, 2018, the following is mentioned about hardware emulation on page 10:

"Hardware Emulation (hw_emu): The kernel code is compiled into a hardware model (RTL) which is run in a dedicated simulator. This build and run loop takes longer but provides a detailed, cycle-accurate, view of kernel activity. This target is useful for testing the functionality of the logic that will go in the FPGA and for getting initial performance estimates."

Can we conclude that performance estimates obtained from hw_emu are realistic?

Regards,

Najeeb Ahmad

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Moderator
Moderator
498 Views
Registered: ‎11-04-2010

Re: Hardware Simulation generating approximate timing

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Hi, @nahmad16,

In my opinion:

The Performance estimation obtained from hw_emu are quite close to the real result, but it cannot be used as a sign-off result. It will be a good guidence for user to understand the whole system performance.

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Don't forget to reply, kudo, and accept as solution.
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Visitor nahmad16
Visitor
490 Views
Registered: ‎10-18-2018

Re: Hardware Simulation generating approximate timing

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Thank you hongh for your assistance.

Regards,

Najeeb Ahmad
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