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Participant gtushar
Participant
1,836 Views
Registered: ‎02-08-2016

How to run the SYCL code on Xilinx FPGA

I am using a simple triSYCL code from Github for vector addition. I am able to execute this code on my CPU. I want to run it on the FPGA.

 

Is there any document guide or any other resource available which I can use to do this?

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7 Replies
Scholar austin
Scholar
1,797 Views
Registered: ‎02-27-2008

Re: How to run the SYCL code on Xilinx FPGA

g,

 

This is a project in Xilinx Research Labs.  Whatever you can find out there that is public you are welcome to.  If you are with a university, you may wish to contact XUP (Xilinx University Program).

Austin Lesea
Principal Engineer
Xilinx San Jose
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Participant gtushar
Participant
1,795 Views
Registered: ‎02-08-2016

Re: How to run the SYCL code on Xilinx FPGA

Austin,

Thanks! Yes I am a student.

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Scholar austin
Scholar
1,788 Views
Registered: ‎02-27-2008

Re: How to run the SYCL code on Xilinx FPGA

Well,

 

Ask your professor if your school is working with us on SYCL.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Participant gtushar
Participant
1,781 Views
Registered: ‎02-08-2016

Re: How to run the SYCL code on Xilinx FPGA

My school is not working with Xilinx.

 

Although, I have sent a request to XUP if they can help me with this topic.

 

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Participant gtushar
Participant
1,530 Views
Registered: ‎02-08-2016

Re: How to run the SYCL code on Xilinx FPGA

 Hi Austin,

I tried to contact the Xilinx University Program but they are not responding at all.

May I ask you if you can help me get a solution for this? a contact perhaps.

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Scholar austin
Scholar
1,527 Views
Registered: ‎02-27-2008

Re: How to run the SYCL code on Xilinx FPGA

XUP responds to professors,

 

You need to ask a faculty member.  Sorry about that, I did not see that you were a student when I suggested XUP contact.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
216 Views
Registered: ‎02-08-2016

Re: How to run the SYCL code on Xilinx FPGA

We are working on a newer approach, since now there are more existing SYCL implementation around: https://github.com/triSYCL/sycl

But as already said, it is a research project and not a supported Xilinx product...

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