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Observer jyerra2
Observer
1,451 Views
Registered: ‎11-01-2017

Launch Simulation Failure for kernel generated using RTL Kernel Wizard

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Hi,

 
I am currently working on porting an existing IP onto the Xilinx VCU1525 platform. It synthesizes correctly in Vivado and I have made the upper-level AXI connections as well using the RTL Kernel Wizard. However, when I try to simulate it to verify functionality, I encounter the following error in the log:
Attached below is the error I encounter.
 
When I tried to search in Google for the answer, I found a solution at https://www.xilinx.com/support/answers/67796.html, however, I am not sure how to change the directory we use or if we should even change it since other files might use the same directory. Could you help me out with a solution for this issue?
 
Sincerely,
Janish Yerra
 
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Observer jyerra2
Observer
1,340 Views
Registered: ‎11-01-2017

回复: Launch Simulation Failure for kernel generated using RTL Kernel Wizard

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Hi,

 

I believe the error has been resolved. I have tried generating another kernel from scratch using the RTL Kernel Wizard. The simulation is successful the first time, but fails if I close the window and start simulation again. This happened the next two times.

 

Then, I tried accessing the RTL Kernel Wizard from the SDAccel Environment rather than through Vivado. The simulation now passes almost every time. I believe this is an error that needs to be fixed by Xilinx.

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Launch Simulation Failure for kernel generated using RTL Kernel Wizard

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The AR is talking about compiled user logic and in your case, the error points to a pre-compiled IP. I'm afraid the AR is not applicable here.

It looks to me you're calling something that is not pre-compiled. I don't see this .sdb file either in the Vivado installation directory.

 

Are you using Vivado 2017.4 within an SDx installation?

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Observer jyerra2
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Registered: ‎11-01-2017

回复: Launch Simulation Failure for kernel generated using RTL Kernel Wizard

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Hi,

 

What does 'AR' mean? I could not find the .sdb file either. I was previously able to run a simulation of a simpler design successfully, but I run into the same error when I try to run the simpler design now. The simulation of that design ran before, but it does not work now. And I have not changed anything in that project. Therefore, I do not understand where it is going wrong.

 

Yes, I am trying to launch the simulation from Vivado 2017.4 with an SDx installation. I do this because I am using the RTL Kernel Wizard to generate an RTL Kernel first.

 

Sincerely,

Janish Yerra

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Launch Simulation Failure for kernel generated using RTL Kernel Wizard

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'AR' means answer record. I was referring to the answer you pointed to.

 

It's strange that a previously working design starts to fail all of a sudden. Do you see the exact same error for the other design? Is it possible to share the test project?

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Observer jyerra2
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Registered: ‎11-01-2017

回复: Launch Simulation Failure for kernel generated using RTL Kernel Wizard

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Sorry no, I will not be able to share the project since it contains the IP of the company I work at. 

 

The module <axi_vip_v1_1_1_top> is not one of ours. My guess is that it would be from the Xilinx IP library since Xilinx makes the AXI connections when it generates an RTL Kernel through the Kernel wizard. It is very weird that this design was working before, but does not work now. Nothing has changed from our side. We had obtained new Xilinx licenses, but when we reverted back to the previous version, we encountered the same error.

 

 

I see a related error for the project that worked before. Attached here is the complete error message:

Vivado Simulator 2017.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: /CADTools/Xilinx/2017.4/Vivado/2017.4/bin/unwrapped/lnx64.o/xelab -wto d91875a6de6a4d24923e9047aabb9c5b --incr --debug typical --relax --mt 8 -L axi_infrastructure_v1_1_0 -L smartconnect_v1_0 -L axi_protocol_checker_v2_0_1 -L xil_defaultlib -L axi_vip_v1_1_1 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot sdx_kernel_wizard_0_exdes_tb_basic_behav xil_defaultlib.sdx_kernel_wizard_0_exdes_tb_basic xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
ERROR: [VRFC 10-2063] Module <axi_vip_v1_1_1_top> not found while processing module instance <inst> [/mnt/DevelopersRAID/user/gary/projects/WORK_xilinx/algo_vcu/vivado_rtl_kernel/sdx_kernel_wizard_0_ex/sdx_kernel_wizard_0_ex.srcs/sources_1/ip/control_sdx_kernel_wizard_0_vip/sim/control_sdx_kernel_wizard_0_vip.sv:120
ERROR: [VRFC 10-2063] Module <slv_m00_axi_vip> not found while processing module instance <inst_slv_m00_axi_vip> [/mnt/DevelopersRAID/user/gary/projects/WORK_xilinx/algo_vcu/vivado_rtl_kernel/sdx_kernel_wizard_0_ex/imports/sdx_kernel_wizard_0_exdes_tb_basic.sv:167
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Launch Simulation Failure for kernel generated using RTL Kernel Wizard

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If you have a previously successful build of the exact same project, you can compare the simulation compile list generated by tool.

Look for .prj within <project dir>/<project>.sim/sim_1/behav/xsim/.

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Observer jyerra2
Observer
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Registered: ‎11-01-2017

回复: Launch Simulation Failure for kernel generated using RTL Kernel Wizard

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Hi,

 

I believe the error has been resolved. I have tried generating another kernel from scratch using the RTL Kernel Wizard. The simulation is successful the first time, but fails if I close the window and start simulation again. This happened the next two times.

 

Then, I tried accessing the RTL Kernel Wizard from the SDAccel Environment rather than through Vivado. The simulation now passes almost every time. I believe this is an error that needs to be fixed by Xilinx.

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787 Views
Registered: ‎11-28-2018

回复: Launch Simulation Failure for kernel generated using RTL Kernel Wizard

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Hi!

I have the same problem:

" ERROR: [VRFC 10-449] cannot open file "/mnt/data/soft/Xilinx/Vivado/2018.2/data/xsim/ip/axi_vip_v1_1_3/axi_vip_v1_1_3_top.sdb" for writing "

I don't understand, how to fix it.

What do you mean under "accessing the RTL Kernel Wizard from the SDAccel Environment rather than through Vivado"

I do it through Vivado, but there is problem

 

Also i found next:

1) i generated RTL kernel with Wizard

2) It prepared RTL wrappers and examples with Adder for me. These files are generated automatically  in folder  /imports

3) I can run Vidao simulation

4) I delete all RTL files and add the same files from /imports folder again

5) Simulation can not start with prevoius error

" ERROR: [VRFC 10-449] cannot open file "/mnt/data/soft/Xilinx/Vivado/2018.2/data/xsim/ip/axi_vip_v1_1_3/axi_vip_v1_1_3_top.sdb" for writing "

 

 

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Registered: ‎11-28-2018

回复: Launch Simulation Failure for kernel generated using RTL Kernel Wizard

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The problem is solved by setting parameter Hierarchy Update to Automatic update and Compiler Order in Vivado.

Now simulation works.

But now Error appears during Emulation-HW.

[

 INFO: [VPL 60-251] Hardware accelerator integration...
ERROR: [VPL 60-399] vivado failed, please see log file for detail: '/home/sadriev/Desktop/projects/fir_cmplx/Emulation-HW/binary_container_1/link/vivado/vivado.log'
ERROR: [VPL 60-806] Failed to finish platform linker
ERROR: [XOCC 60-398] vpl failed
ERROR: [XOCC 60-626] Kernel link failed to complete
ERROR: [XOCC 60-703] Failed to finish linking
makefile:77: recipe for target 'binary_container_1.xclbin' failed
make: *** [binary_container_1.xclbin] Error 1

]

Message send to Emulation-HW/binary_container_1/link/vivado/vivado.log

[

launch_simulation: Time (s): cpu = 00:00:09 ; elapsed = 00:00:28 . Memory (MB): peak = 2375.145 ; gain = 17.484 ; free physical = 4410 ; free virtual = 34481
INFO: [Vivado 12-5680] Creating behavioral simulation scripts in '/home/sadriev/Desktop/projects/fir_cmplx/Emulation-HW/binary_container_1/link/vivado/prj/prj.sim/sim_1/behav/xsim'
INFO: [Vivado 12-5425] Xilinx recommends using the export_simulation Tcl command for generating simulation scripts to use outside of the Vivado environment. Please see 'Logic Simulation' user guide UG900 for details on how to use this command.
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/mnt/data/soft/Xilinx/Vivado/2018.2/data/xsim/xsim.ini' copied to run dir:'/home/sadriev/Desktop/projects/fir_cmplx/Emulation-HW/binary_container_1/link/vivado/prj/prj.sim/sim_1/behav/xsim'
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-60] Script generated:/home/sadriev/Desktop/projects/fir_cmplx/Emulation-HW/binary_container_1/link/vivado/prj/prj.sim/sim_1/behav/xsim/compile.sh
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-60] Script generated:/home/sadriev/Desktop/projects/fir_cmplx/Emulation-HW/binary_container_1/link/vivado/prj/prj.sim/sim_1/behav/xsim/elaborate.sh
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-60] Script generated:/home/sadriev/Desktop/projects/fir_cmplx/Emulation-HW/binary_container_1/link/vivado/prj/prj.sim/sim_1/behav/xsim/simulate.sh
launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 2375.145 ; gain = 0.000 ; free physical = 4306 ; free virtual = 33204
error renaming "simulate_sysemulation.sh" to "simulate.sh": no such file or directory
while executing
"file rename -force simulate_sysemulation.sh simulate.sh"
(procedure "writeNewSimulateScript" line 13)
invoked from within
"writeNewSimulateScript $replaceXSimCall $bdName"
(procedure "hw_em_common_util::generate_simulation_scripts_and_compile" line 118)
invoked from within
"hw_em_common_util::generate_simulation_scripts_and_compile $config_info"
(procedure "hw_em_util::generate_simulation_scripts_and_compile" line 2)
invoked from within
"hw_em_util::generate_simulation_scripts_and_compile $config_info"
(file "/home/sadriev/Desktop/projects/fir_cmplx/Emulation-HW/binary_container_1/link/vivado/ipirun.tcl" line 202)
INFO: [Common 17-206] Exiting Vivado at Wed Nov 28 18:10:31 2018...

 ]

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Registered: ‎11-28-2018

回复: Launch Simulation Failure for kernel generated using RTL Kernel Wizard

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Any idea how to fix it? 

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