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Observer skotti
Observer
576 Views
Registered: ‎06-18-2018

New version of SDAccel 2018.2 performs internal transformations

Hello!

I have this bunch of code:

#pragma OPENCL EXTENSION cl_khr_fp64 : enable

__kernel void kernel0(__global double *A, __global double *B, int tsteps, int n, int c0)
{
    int b0 = get_group_id(0);
    int t0 = get_local_id(0);

    local double local_A[30]  __attribute__((xcl_array_partition(cyclic,2,1)));
    local double local_B[30]  __attribute__((xcl_array_partition(cyclic,2,1)));

#pragma nounroll
    for (int i = 0; i < 30; i++) {
    	local_A[i] = A[i];
        local_B[i] = B[i];
    }

    for (int c1 = 1; c1 < n - 1; c1 += 1) {
    	local_B[c1] = (0.33333 * ((local_A[c1 - 1] + local_A[c1]) + local_A[c1 + 1]));
    }

#pragma nounroll
    for (int i = 0; i < 30; i++) {
        A[i] = local_A[i];
    	B[i] = local_B[i];
    }
}
__kernel void kernel1(__global double *A, __global double *B, int tsteps, int n, int c0)
{
    int b0 = get_group_id(0);
    int t0 = get_local_id(0);

    for (int c1 = 1; c1 < n - 1; c1 += 1)
      A[c1] = (0.33333 * ((B[c1 - 1] + B[c1]) + B[c1 + 1]));
}

I mapped A and B to different banks (0, 1) in the host code.

SDAccel process this kernel and instead of reporting three kernels with II=1 creates five (!!) cycles with II=1. Why does this happen? In 2018.1 I didn't have such problems.

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1 Reply
Xilinx Employee
Xilinx Employee
481 Views
Registered: ‎06-17-2008

Re: New version of SDAccel 2018.2 performs internal transformations

Could you try placing the pipeline attribute before the loop and see if behavior changes?

__attribute__((xcl_pipeline_loop))

for () {

}

 

If II still can not meet the target, you may open the corresponding HLS project and use analysis view to identify the root cause.